公开(公告)号：US11621049B2

公开(公告)日：2023-04-04

申请号：US17397213

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Venkata Naga Lakshman Pasala ,  Wei Wang ,  Jiangli Zhu

IPC: G11C29/42 ,  G11C29/40 ,  G11C7/02 ,  G11C29/44 ,  G11C29/12

Abstract: A system include multiple memory dice and a processing device coupled to the multiple memory dice. The processing device is to perform operations, including: reading temperature values from registers at multiple memory dice, wherein each temperature value is associated with a temperature at a respective die of the multiple memory dice; reading error-correcting code (ECC)-protected data from the multiple memory dice; determining whether an ECC check of the ECC-protected data results in detecting an error; in response to detecting the error from the ECC-protected data for a die of the multiple memory dice, performing a confirmation check that the error is a result of a defect in the die; and in response to the confirmation check confirming the die is defective, ignoring a temperature value from the die when determining whether to trigger a thermal-related operation.

公开(公告)号：US20220283744A1

公开(公告)日：2022-09-08

申请号：US17703902

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US20220155840A1

公开(公告)日：2022-05-19

申请号：US16949892

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Frederick Adi ,  Venkata Naga Lakshman Pasala ,  Wei Wang ,  Jiangli Zhu ,  Paul Stonelake ,  Nagireddy Chodem

IPC: G06F1/30 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/07

Abstract: A processing device in a memory sub-system detects a preemptive power loss condition in the memory sub-system and, in response, causes operations of a local media controller associated with a memory device in the memory sub-system to be suspended, wherein responsive to being suspended, the local media controller to perform power loss handling operations to complete a subset of a plurality of pending memory access operations, and wherein to perform the power loss handling operations, the local media controller to complete the subset of the plurality of pending memory access operations for which an acknowledgment signal has been sent to a requestor. The processing device further detects a full power loss and restore condition in the memory sub-system, responsive to detecting the full power loss and restore condition, initializes the memory device and causes operations of the local media controller to resume.

公开(公告)号：US11288013B2

公开(公告)日：2022-03-29

申请号：US16916934

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Yu Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US20210271421A1

公开(公告)日：2021-09-02

申请号：US17303169

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Wei Wang ,  Ying Yu Tai ,  Jason Duong ,  Chih-Kuo Kao

IPC: G06F3/06

Abstract: A processing device in a memory system determines that a number of commands from an active queue that have been executed on a memory device does not satisfy an executed transaction threshold criterion, that a number of pending commands in an inactive queue satisfies a first promotion threshold criterion, and that a number of pending commands in the active queue does not satisfy a second promotion threshold criterion. In response, the processing device switches an execution grant from the active queue to the inactive queue.

公开(公告)号：US20210019217A1

公开(公告)日：2021-01-21

申请号：US16784966

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Ying Yu Tai ,  Fangfang Zhu ,  Wei Wang

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/30 ,  G06F9/54 ,  G06F9/30

Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.