公开(公告)号：US20230090523A1

公开(公告)日：2023-03-23

申请号：US18071930

申请日：2022-11-30

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Tingjun Xie ,  Wei Wang ,  Frederick Adi ,  Zhenming Zhou ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A current cycle count associated with a memory sub-system is determined. The current cycle count is compared to a set of cycle count threshold levels to determine a current lifecycle stage of the memory sub-system. A temperature associated with the memory sub-system is measured. The temperature is compared to a set of temperature levels to determine a current temperature level of the memory sub-system. A write-to-read delay time corresponding to the current lifecycle stage and the current temperature level is determined.

公开(公告)号：US11520657B1

公开(公告)日：2022-12-06

申请号：US17445392

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  Tingjun Xie ,  Frederick Adi ,  Wei Wang ,  Zhenming Zhou

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

公开(公告)号：US11526295B2

公开(公告)日：2022-12-13

申请号：US16934406

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Tingjun Xie ,  Wei Wang ,  Frederick Adi ,  Zhenming Zhou ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A first operating characteristic and a second operating characteristic of a memory sub-system are determined. A write-to-read delay time is set in view of the first operating characteristic and the second operating characteristic. A read operation associated with a memory unit is executed following a period of at least the write-to-read delay time from a time of an execution of a write operation associated with the memory unit.

公开(公告)号：US20220100605A1

公开(公告)日：2022-03-31

申请号：US17445345

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Frederick Adi ,  Zhenlei Shen ,  Wei Wang

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.

公开(公告)号：US20220027077A1

公开(公告)日：2022-01-27

申请号：US16934406

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Tingjun Xie ,  Wei Wang ,  Frederick Adi ,  Zhenming Zhou ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A first operating characteristic and a second operating characteristic of a memory sub-system are determined. A write-to-read delay time is set in view of the first operating characteristic and the second operating characteristic. A read operation associated with a memory unit is executed following a period of at least the write-to-read delay time from a time of an execution of a write operation associated with the memory unit.

公开(公告)号：US11782831B2

公开(公告)日：2023-10-10

申请号：US17464350

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Huapeng G. Guan ,  Frederick Adi ,  Jiangli Zhu ,  Yipei Yu ,  Venkata Naga Lakshman Pasala ,  Wei Wang

IPC: G06F12/0804 ,  G06F12/1009

CPC classification number: G06F12/0804 ,  G06F12/1009 ,  G06F2212/1032 ,  G06F2212/657

Abstract: A system for managing power loss can include a number of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices. The processor can save a snapshot of a logical-to-physical (L2P) table to a non-volatile memory device and maintain a journal of updates of the L2P. The processor can, in response to a parameter of journal buffer of a volatile memory device satisfying a threshold criterion, save at least one journal of updates of the L2P table to the non-volatile memory device. It can also retrieve a sequence number from system metadata and save the most recent set of updates of the L2P table to a dedicated area of the non-volatile memory device, where the dedicated area is identified by the sequence number, in response to detecting a power loss event.

公开(公告)号：US11775388B2

公开(公告)日：2023-10-03

申请号：US17972230

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  Tingjun Xie ,  Frederick Adi ,  Wei Wang ,  Zhenming Zhou

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0757 ,  G06F11/0772

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

公开(公告)号：US11709538B2

公开(公告)日：2023-07-25

申请号：US16949892

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Frederick Adi ,  Venkata Naga Lakshman Pasala ,  Wei Wang ,  Jiangli Zhu ,  Paul Stonelake ,  Nagireddy Chodem

IPC: G06F11/00 ,  G06F1/30 ,  G06F1/3234 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F1/30 ,  G06F1/3275 ,  G06F11/0772 ,  G06F11/3037 ,  G06F11/3062

Abstract: A processing device in a memory sub-system detects a preemptive power loss condition in the memory sub-system and, in response, causes operations of a local media controller associated with a memory device in the memory sub-system to be suspended, wherein responsive to being suspended, the local media controller to perform power loss handling operations to complete a subset of a plurality of pending memory access operations, and wherein to perform the power loss handling operations, the local media controller to complete the subset of the plurality of pending memory access operations for which an acknowledgment signal has been sent to a requestor. The processing device further detects a full power loss and restore condition in the memory sub-system, responsive to detecting the full power loss and restore condition, initializes the memory device and causes operations of the local media controller to resume.

公开(公告)号：US11656938B2

公开(公告)日：2023-05-23

申请号：US17445345

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Frederick Adi ,  Zhenlei Shen ,  Wei Wang

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076

Abstract: A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.

公开(公告)号：US20220155840A1

公开(公告)日：2022-05-19

申请号：US16949892

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Frederick Adi ,  Venkata Naga Lakshman Pasala ,  Wei Wang ,  Jiangli Zhu ,  Paul Stonelake ,  Nagireddy Chodem

IPC: G06F1/30 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/07

Abstract: A processing device in a memory sub-system detects a preemptive power loss condition in the memory sub-system and, in response, causes operations of a local media controller associated with a memory device in the memory sub-system to be suspended, wherein responsive to being suspended, the local media controller to perform power loss handling operations to complete a subset of a plurality of pending memory access operations, and wherein to perform the power loss handling operations, the local media controller to complete the subset of the plurality of pending memory access operations for which an acknowledgment signal has been sent to a requestor. The processing device further detects a full power loss and restore condition in the memory sub-system, responsive to detecting the full power loss and restore condition, initializes the memory device and causes operations of the local media controller to resume.