公开(公告)号：US06720642B1

公开(公告)日：2004-04-13

申请号：US09464885

申请日：1999-12-16

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23495

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US08212361B2

公开(公告)日：2012-07-03

申请号：US12575641

申请日：2009-10-08

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L23/48

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US20100090331A1

公开(公告)日：2010-04-15

申请号：US12575641

申请日：2009-10-08

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US07632719B2

公开(公告)日：2009-12-15

申请号：US12350065

申请日：2009-01-07

Applicant: Seung Yong Choi ,  Min Hyo Park ,  Ji Hwan Kim ,  Rajeev Joshi

Inventor： Seung Yong Choi ,  Min Hyo Park ,  Ji Hwan Kim ,  Rajeev Joshi

IPC: H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

Abstract translation: 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US20090186452A1

公开(公告)日：2009-07-23

申请号：US12357981

申请日：2009-01-22

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC: H01L21/50

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05124

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract translation: 公开了一种用于形成螺柱凸起的半导体管芯的方法。 该方法包括在穿过毛细管中的孔的涂覆线的尖端处形成球，其中涂覆线具有芯和抗氧化涂层。 将形成的球按压到半导体管芯上的导电区域。 涂覆的线材被切割，从而在导电区域上留下导电柱状凸块，其中导电柱形凸块包括内部导电部分和外部抗氧化层。

公开(公告)号：US07537958B1

公开(公告)日：2009-05-26

申请号：US11283077

申请日：2005-11-18

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

公开(公告)号：US20090111219A1

公开(公告)日：2009-04-30

申请号：US12350065

申请日：2009-01-07

Applicant: Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

Inventor： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

IPC: H01L21/50

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

Abstract translation: 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US07501337B2

公开(公告)日：2009-03-10

申请号：US11404650

申请日：2006-04-14

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC: H01L21/44

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05124

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract translation: 公开了一种用于形成螺柱凸起的半导体管芯的方法。 该方法包括在穿过毛细管中的孔的涂覆线的尖端处形成球，其中涂覆线具有芯和抗氧化涂层。 将形成的球按压到半导体管芯上的导电区域。 涂覆的线材被切割，从而在导电区域上留下导电柱状凸块，其中导电柱形凸块包括内部导电部分和外部抗氧化层。

公开(公告)号：US20080213946A1

公开(公告)日：2008-09-04

申请号：US12118222

申请日：2008-05-09

Applicant: Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

Inventor： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC: H01L21/60

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯位于管芯附着区域上，半导体管芯与引线电耦合。 管芯附着表面和引线表面可以在不同的平面上。

公开(公告)号：US20080190480A1

公开(公告)日：2008-08-14

申请号：US12069094

申请日：2008-02-06

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L31/0203 ,  H01L31/0232 ,  H01L31/024 ,  H01L31/18

CPC classification number: H01L31/044 ,  H01L31/052 ,  H01L31/0521 ,  H01L31/054 ,  H01L31/0543 ,  Y02E10/52 ,  Y10T29/49002

Abstract: A leadframe based photovoltaic assembly and method for assembling the same is disclosed. The photovoltaic assembly comprises a first and second mold compounds to effectuate the accurate placement of an optical concentrator above a photovoltaic cell. The photovoltaic assembly is able to be assembled using existing mature semiconductor packaging technologies.

Abstract translation: 公开了一种基于引线框架的光伏组件及其组装方法。 光伏组件包括第一和第二模具化合物，以实现光聚焦器在光伏电池上方的精确放置。 光伏组件能够使用现有的成熟半导体封装技术进行组装。