Test access port and TCK inverter for shadow access port

    公开(公告)号:US10054639B2

    公开(公告)日:2018-08-21

    申请号:US15609950

    申请日:2017-05-31

    Inventor: Lee D. Whetsel

    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

    TAP and auxiliary circuitry with auxiliary output multiplexer and buffers

    公开(公告)号:US09759771B2

    公开(公告)日:2017-09-12

    申请号:US15346110

    申请日:2016-11-08

    Inventor: Lee D. Whetsel

    CPC classification number: G01R31/318558 G01R31/318536 G01R31/318572

    Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

    ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION

    公开(公告)号:US20170248656A1

    公开(公告)日:2017-08-31

    申请号:US15593834

    申请日:2017-05-12

    Inventor: Lee D. Whetsel

    Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

    METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION

    公开(公告)号:US20170242074A1

    公开(公告)日:2017-08-24

    申请号:US15591750

    申请日:2017-05-10

    Inventor: Lee D. Whetsel

    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

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