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公开(公告)号:US10068816B2
公开(公告)日:2018-09-04
申请号:US15788282
申请日:2017-10-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/02 , H01L21/66 , H01L23/48 , G01R31/28 , G01R31/3185 , H01L25/065
Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.
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公开(公告)号:US10054639B2
公开(公告)日:2018-08-21
申请号:US15609950
申请日:2017-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/3177 , G01R31/3185
CPC classification number: G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318555
Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
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公开(公告)号:US10036776B2
公开(公告)日:2018-07-31
申请号:US15871602
申请日:2018-01-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/267 , G01R31/3177
CPC classification number: G01R31/31723 , G01R31/317 , G01R31/31705 , G01R31/31727 , G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318591 , G01R31/318597 , G06F11/267
Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
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公开(公告)号:US09939489B2
公开(公告)日:2018-04-10
申请号:US15359785
申请日:2016-11-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/28 , G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/3173
CPC classification number: G01R31/31723 , G01R31/2851 , G01R31/3172 , G01R31/31724 , G01R31/3173 , G01R31/3177 , G01R31/318563 , G01R31/318575
Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.
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公开(公告)号:US09897654B2
公开(公告)日:2018-02-20
申请号:US15419379
申请日:2017-01-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/3187 , G06F1/32 , G01R31/28
CPC classification number: G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
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公开(公告)号:US20170285103A1
公开(公告)日:2017-10-05
申请号:US15622840
申请日:2017-06-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/3177 , G01R31/317 , G01R31/3185
CPC classification number: G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318536 , G01R31/318572 , G01R31/318577
Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
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公开(公告)号:US09759771B2
公开(公告)日:2017-09-12
申请号:US15346110
申请日:2016-11-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/3185
CPC classification number: G01R31/318558 , G01R31/318536 , G01R31/318572
Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
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公开(公告)号:US20170248656A1
公开(公告)日:2017-08-31
申请号:US15593834
申请日:2017-05-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/3185 , G01R31/3177 , G01R31/317
CPC classification number: G01R31/318536 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G01R31/318575 , G01R31/318577
Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
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公开(公告)号:US20170242074A1
公开(公告)日:2017-08-24
申请号:US15591750
申请日:2017-05-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318533
Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
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公开(公告)号:US09720039B2
公开(公告)日:2017-08-01
申请号:US15359124
申请日:2016-11-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Lee D. Whetsel
IPC: G01R31/317 , G01R31/3177 , G01R31/3185 , G01R31/28 , G01R31/3183
CPC classification number: G01R31/31723 , G01R31/2896 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/3183 , G01R31/318513 , G01R31/318552 , G01R31/318555 , G01R31/318558 , G01R31/318572 , G01R31/318594
Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
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