公开(公告)号：US09756351B2

公开(公告)日：2017-09-05

申请号：US15257550

申请日：2016-09-06

Applicant: Texas Instruments Incorporated

Inventor： Mihir Mody

IPC: H04N19/436 ,  H04N19/119 ,  H04N19/156 ,  H04N19/174 ,  H04N19/423 ,  H04N19/82

CPC classification number: H04N19/436 ,  H04N19/119 ,  H04N19/156 ,  H04N19/174 ,  H04N19/423 ,  H04N19/82

Abstract: The disclosure provides a video encoder. The video encoder receives a frame and divides the frame into a plurality of tiles. The video encoder includes a plurality of video processing engines communicatively coupled with each other. Each video processing engine receives a tile of the plurality of tiles. A height of each tile is equal to a height of the frame and each tile comprises a plurality of rows. The plurality of video processing engines includes a first and a second video processing engine. The second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.

公开(公告)号：US20150339234A1

公开(公告)日：2015-11-26

申请号：US14583020

申请日：2014-12-24

Applicant: Texas Instruments Incorporated

Inventor： Prashant Dinkar Karandikar ,  Mihir Mody ,  Hetul Sanghavi ,  Vasant Easwaran ,  Prithvi Y.A. Shankar ,  Rahul Gulati ,  Niraj Nandan ,  Subrangshu Das

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F3/06 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/601 ,  G06F2212/602

Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.

Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。