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公开(公告)号：US09430393B2
公开(公告)日：2016-08-30
申请号：US14583020
申请日：2014-12-24
Applicant: Texas Instruments Incorporated
Inventor： Prashant Dinkar Karandikar , Mihir Mody , Hetul Sanghavi , Vasant Easwaran , Prithvi Y. A. Shankar , Rahul Gulati , Niraj Nandan , Subrangshu Das
CPC classification number: G06F12/0862 , G06F3/06 , G06F12/08 , G06F12/0888 , G06F2212/601 , G06F2212/602
Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。
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公开(公告)号：US11662211B2
公开(公告)日：2023-05-30
申请号：US16983437
申请日：2020-08-03
Applicant: Texas Instruments Incorporated
Inventor： Rahul Gulati , Aishwarya Dubey , Nainala Vyagrheswarudu , Vasant Easwaran , Prashant Dinkar Karandikar , Mihir Mody
CPC classification number: G01C21/206 , G06F11/10 , G06F2201/845
Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.
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公开(公告)号：US20150212955A1
公开(公告)日：2015-07-30
申请号：US14603609
申请日：2015-01-23
Applicant: Texas Instruments Incorporated
Inventor： Vasant Easwaran
CPC classification number: G06F13/24 , G06F13/287 , G06F13/4022
Abstract: A multiprocessor device is provided that includes a plurality of processors in which each processor of the plurality of processors includes an interrupt controller, and a symmetric interrupt crossbar having a plurality of interrupt inputs in which each interrupt input that is not reserved is coupled to a respective interrupt output of an interrupt source of a plurality of interrupt sources, and a plurality of interrupt outputs in which each interrupt output is coupled to a respective interrupt input of an interrupt controller of one of the plurality of processors, in which the symmetric interrupt crossbar is programmable to map an interrupt signal from any interrupt source of the plurality of interrupt sources coupled to the symmetric interrupt crossbar to any interrupt input of any interrupt controller coupled to the symmetric interrupt crossbar.
Abstract translation: 提供了一种多处理器装置，其包括多个处理器，其中多个处理器中的每个处理器包括中断控制器，以及具有多个中断输入的对称中断交叉开关，其中每个不预留的中断输入被耦合到相应的 多个中断源的中断源的中断输出和多个中断输出，其中每个中断输出耦合到多个处理器之一的中断控制器的相应中断输入，其中对称中断横向是 可编程为将来自耦合到对称中断交叉开关的多个中断源的任何中断源的中断信号映射到耦合到对称中断交叉开关的任何中断控制器的任何中断输入。
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公开(公告)号：US10767998B2
公开(公告)日：2020-09-08
申请号：US16114419
申请日：2018-08-28
Applicant: Texas Instruments Incorporated
Inventor： Rahul Gulati , Aishwarya Dubey , Nainala Vyagrheswarudu , Vasant Easwaran , Prashant Dinkar Karandikar , Mihir Mody
Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.
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公开(公告)号：US20180364051A1
公开(公告)日：2018-12-20
申请号：US16114419
申请日：2018-08-28
Applicant: Texas Instruments Incorporated
Inventor： Rahul Gulati , Aishwarya Dubey , Nainala Vyagrheswarudu , Vasant Easwaran , Prashant Dinkar Karandikar , Mihir Moody
IPC: G01C21/20
CPC classification number: G01C21/206 , G06F11/10 , G06F2201/845
Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.
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Patent Agency Ranking
公开(公告)号：US10089172B2
公开(公告)日：2018-10-02
申请号：US14587878
申请日：2014-12-31
Applicant: Texas Instruments Incorporated
Inventor： Rahul Gulati , Aishwarya Dubey , Nainala Vyagrheswarudu , Vasant Easwaran , Prashant Dinkar Karandikar , Mihir Mody
Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.
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公开(公告)号：US09628787B2
公开(公告)日：2017-04-18
申请号：US14607053
申请日：2015-01-27
Applicant: Texas Instruments Incorporated
Inventor： Rahul Gulati , Vasant Easwaran , Mihir Narendra Mody , Prashant Dinkar Karandikar , Prithvi Y. A. Shankar , Aishwarya Dubey , Kedar Chitnis , Rajat Sagar
CPC classification number: H04N17/002 , G06T7/0002 , G06T2207/30168 , G06T2207/30252
Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.
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公开(公告)号：US20150339234A1
公开(公告)日：2015-11-26
申请号：US14583020
申请日：2014-12-24
Applicant: Texas Instruments Incorporated
Inventor： Prashant Dinkar Karandikar , Mihir Mody , Hetul Sanghavi , Vasant Easwaran , Prithvi Y.A. Shankar , Rahul Gulati , Niraj Nandan , Subrangshu Das
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F3/06 , G06F12/08 , G06F12/0888 , G06F2212/601 , G06F2212/602
Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。
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公开(公告)号：US20230258454A1
公开(公告)日：2023-08-17
申请号：US18306510
申请日：2023-04-25
Applicant: Texas Instruments Incorporated
Inventor： Rahul Gulati , Aishwarya Dubey , Nainala Vyagrheswarudu , Vasant Easwaran , Prashant Dinkar Karandikar , Mihir Mody
CPC classification number: G01C21/206 , G06F11/10 , G06F2201/845
Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.
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公开(公告)号：US09442869B2
公开(公告)日：2016-09-13
申请号：US14603609
申请日：2015-01-23
Applicant: Texas Instruments Incorporated
Inventor： Vasant Easwaran
CPC classification number: G06F13/24 , G06F13/287 , G06F13/4022
Abstract: A multiprocessor device is provided that includes a plurality of processors in which each processor of the plurality of processors includes an interrupt controller, and a symmetric interrupt crossbar having a plurality of interrupt inputs in which each interrupt input that is not reserved is coupled to a respective interrupt output of an interrupt source of a plurality of interrupt sources, and a plurality of interrupt outputs in which each interrupt output is coupled to a respective interrupt input of an interrupt controller of one of the plurality of processors, in which the symmetric interrupt crossbar is programmable to map an interrupt signal from any interrupt source of the plurality of interrupt sources coupled to the symmetric interrupt crossbar to any interrupt input of any interrupt controller coupled to the symmetric interrupt crossbar.
Abstract translation: 提供了一种多处理器装置，其包括多个处理器，其中多个处理器中的每个处理器包括中断控制器，以及具有多个中断输入的对称中断交叉开关，其中每个不预留的中断输入被耦合到相应的 多个中断源的中断源的中断输出和多个中断输出，其中每个中断输出耦合到多个处理器之一的中断控制器的相应中断输入，其中对称中断横向是 可编程为将来自耦合到对称中断交叉开关的多个中断源的任何中断源的中断信号映射到耦合到对称中断交叉开关的任何中断控制器的任何中断输入。
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