公开(公告)号：US11862622B2

公开(公告)日：2024-01-02

申请号：US17348784

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Chien-Hung Chen ,  Chun-Hsien Lin

IPC: H01L27/02 ,  H03K19/20

CPC classification number: H01L27/0207 ,  H03K19/20

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

公开(公告)号：US20230207648A1

公开(公告)日：2023-06-29

申请号：US17583225

申请日：2022-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  G11C5/063 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/7851

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20230099326A1

公开(公告)日：2023-03-30

申请号：US17869797

申请日：2022-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/118 ,  G06F30/392

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

公开(公告)号：US11532716B2

公开(公告)日：2022-12-20

申请号：US16793930

申请日：2020-02-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen Yang Hsueh ,  Ling Hsiu Chou ,  Chih-Yang Hsu

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66 ,  G11C16/16 ,  G11C16/14

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

公开(公告)号：US20210391339A1

公开(公告)日：2021-12-16

申请号：US16923117

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/8238

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20210366913A1

公开(公告)日：2021-11-25

申请号：US16905883

申请日：2020-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chien-Hung Chen

IPC: H01L27/11

Abstract: A static random access memory (SRAM) includes a substrate having a first active region and a second active region adjacent to the first active region. A first gate structure is disposed on the substrate and across the first active region and the second active region. A second gate structure is adjacent to a first side of the first gate structure. A first lower contact structure is disposed on the first active region and adjacent to a second side of the first gate structure. A first upper contact structure is disposed on and in direct contact with the first lower contact structure. A top surface of the first lower contact structure and a sidewall of the first upper contact structure comprise a step profile therebetween.

公开(公告)号：US11018132B2

公开(公告)日：2021-05-25

申请号：US16380953

申请日：2019-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L27/06 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11541 ,  H01L27/11543 ,  H01L21/311 ,  H01L21/285

Abstract: A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate.

公开(公告)号：US20200057966A1

公开(公告)日：2020-02-20

申请号：US16105182

申请日：2018-08-20

Applicant: United Microelectronics Corp.

Inventor： Yao-Sheng Chang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Da-Ching Liao

IPC: G06N99/00 ,  G06F5/01 ,  G06F17/16

Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

公开(公告)号：US10134449B2

公开(公告)日：2018-11-20

申请号：US15589985

申请日：2017-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

IPC: G11C5/02 ,  G11C11/412 ,  H01L27/11

Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

公开(公告)号：US20170200721A1

公开(公告)日：2017-07-13

申请号：US15045258

申请日：2016-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Chia-Hsun Tseng ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.