公开(公告)号：US20170062282A1

公开(公告)日：2017-03-02

申请号：US15352605

申请日：2016-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了包括多个隔离结构的基板。 第一nFET器件和第二nFET器件形成在衬底上。 第一nFET器件包括第一栅极沟槽，第二nFET包括第二栅极沟槽。 在第一栅极沟槽中形成第三底部阻挡层，同时在第二栅极沟槽中形成第三p功函数金属层。 第三底部阻挡层和第三p功函数金属层包括相同的材料。 在第一栅极沟槽和第二栅极沟槽中形成n功函数金属层。 第一栅极沟槽中的n功函数金属层直接接触第三底部势垒层，并且第二栅极沟槽中的n功函数金属层直接接触第三p功函数金属层。

公开(公告)号：US20160225662A1

公开(公告)日：2016-08-04

申请号：US14612235

申请日：2015-02-02

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在ILD层和栅极结构上形成介电层; 在介电层和ILD层中形成开口; 在介质层和开口中形成有机介电层（ODL）; 去除部分ODL; 去除用于延伸开口的电介质层的一部分; 去除剩余的ODL; 并在开口中形成接触塞。