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    Window-type semiconductor package to avoid peeling at moldflow entrance
    64.
    发明授权
    Window-type semiconductor package to avoid peeling at moldflow entrance 有权
    窗型半导体封装，避免模具流入口剥离

    公开(公告)号：US07633160B1

    公开(公告)日：2009-12-15

    申请号：US12269440

    申请日：2008-11-12

    Applicant: Chuang-Fa Lee ,  Chao-Hsiang Leu ,  Tseng-Shin Chiu

    Inventor： Chuang-Fa Lee ,  Chao-Hsiang Leu ,  Tseng-Shin Chiu

    IPC: H01L23/498

    CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A window-type semiconductor package is disclosed to avoid peeling at the moldflow entrance, primarily comprising a substrate, a chip with the active surface attached to the substrate, a die-attaching layer bonding the active surface of the chip to a substrate core of the substrate, a plurality of bonding wires, and an encapsulant. The substrate core has a slot. One end of the slot outside the chip is formed as a moldflow entrance with two or more moldflow blocking lumps protrusively disposed on the substrate core and located at the intersections between one edge of the chip and the two opposing sides of the slot adjacent to the moldflow entrance. Accordingly, the moldflow pressures exerting at the die-attaching layer are blocked to avoid the peeling of the die-attaching layer at the moldflow entrance and to keep a constant die-attaching gap.

    Abstract translation: 公开了一种窗型半导体封装，以避免在模流入口处的剥离，主要包括基板，具有附着到基板的活性表面的芯片，将芯片的有源表面粘合到芯片的基板芯的芯片附着层 基板，多根接合线和密封剂。 衬底芯具有槽。 芯片外部的槽的一端形成为具有两个或更多个模流阻塞块的模流入口，该两个或更多个模流阻塞块突出地设置在衬底芯上，并且位于芯片的一个边缘和与模流相邻的槽的两个相对侧 入口。 因此，在模具附着层施加的模具流动压力被阻挡，以避免模具附着层在模具流入口处的剥离，并且保持恒定的模具附着间隙。

    Method for Fabricating Semiconductor Elements
    65.
    发明申请
    Method for Fabricating Semiconductor Elements 审中-公开
    半导体元件制造方法

    公开(公告)号：US20090298233A1

    公开(公告)日：2009-12-03

    申请号：US12240499

    申请日：2008-09-29

    Applicant: Chin-Ti Chen

    Inventor： Chin-Ti Chen

    IPC: H01L21/56

    CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L2224/73203

    Abstract: The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements.

    Abstract translation: 本发明公开了一种制造半导体元件的方法，包括以下步骤：在其上表面上提供具有布线图案的基板，将晶片与基板电连接以进行信号输入和输出; 将树脂填充到晶片和轮胎基板之间以将晶片固定到基板; 以及将晶片和衬底的组合分离成多个半导体元件。 因此，本发明可以简化制造工艺或半导体元件。

    Lead Frame and Chip Package Structure and Method for Fabricating the Same
    66.
    发明申请
    Lead Frame and Chip Package Structure and Method for Fabricating the Same 审中-公开
    引线框架和芯片封装结构及其制造方法

    公开(公告)号：US20090294933A1

    公开(公告)日：2009-12-03

    申请号：US12240362

    申请日：2008-09-29

    Applicant: Chin-Ti Chen

    Inventor： Chin-Ti Chen

    IPC: H01L23/495 ,  H01L21/00

    CPC classification number: H01L23/49575 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted.

    Abstract translation: 本发明公开了一种引线框架和芯片封装结构，其包括多个引线，其包括多个内引线和多个外引线; 布置在所述内引线的一部分上的多个芯片; 多个连接线将芯片电连接到其它内部引线; 支撑构件，其布置在所述内引线的下表面上并且具有带开口的填充物，其中所述开口的所述背面面向所述内引线; 以及覆盖引线，芯片，连接线和支撑构件的树脂密封剂，并且用外部引线的一部分填充填充物，并且露出支撑构件的表面的一部分。 此外，本发明还公开了一种用于制造引线框架和芯片封装结构的方法，从而促进了芯片封装的质量。

    COL (Chip-On-Lead) multi-chip package
    67.
    发明授权
    COL (Chip-On-Lead) multi-chip package 有权
    COL（Chip-On-Lead）芯片封装

    公开(公告)号：US07622794B1

    公开(公告)日：2009-11-24

    申请号：US12133892

    申请日：2008-06-05

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/495

    CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

    Abstract: A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, the thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.

    Abstract translation: 揭示了芯片引线（COL）多芯片封装，主要包括多个引线，设置在第一引线上的第一芯片，堆叠在第一芯片上的一个或多个第二芯片和密封剂。 引线具有封装在密封剂内部的多个内部引线，其中内部引线完全形成在朝向并平行于密封剂的底表面的凹陷平面上。 位于密封剂顶表面的内部引线之间的高度是内部引线和底部表面之间的高度的三倍或更大。 由于第二芯片的数量和厚度受到控制，所以密封剂的顶表面与最邻近的第二芯片之间的厚度与密封剂的内部引线和底部表面之间的厚度大致相同 。 因此，密封剂中引线没有下弯曲的内部引线可平衡上下模流，并承载更多的芯片而不会移位或倾斜。

    LEAD-ON-CHIP SEMICONDUCTOR PACKAGE AND LEADFRAME FOR THE PACKAGE
    68.
    发明申请
    LEAD-ON-CHIP SEMICONDUCTOR PACKAGE AND LEADFRAME FOR THE PACKAGE 失效
    引线芯片半导体封装和封装的引线框架

    公开(公告)号：US20090283878A1

    公开(公告)日：2009-11-19

    申请号：US12122946

    申请日：2008-05-19

    Applicant: Wen-Jeng FAN ,  Yu-Mei HSU

    Inventor： Wen-Jeng FAN ,  Yu-Mei HSU

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

    Abstract: A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads.

    Abstract translation: 显示了具有封装引线框的LOC半导体封装。 LOC半导体封装主要包括多个引线框的引线，至少一个连接条，芯片和封装上述部件的密封剂。 每个引线都有一个粘结手指。 连接杆具有虚拟手指，其中虚拟手指线性地设置在接合指的配置区域的一侧。 该芯片具有带有接合指状物的活性表面。 当虚设手指和结合指状物通过管芯附着层设置在有效表面上方时，虚拟手指与活动表面的一个边缘相邻。 接合指状物与接合焊盘电连接。 虚拟手指将承受集中应力，以避免活动表面上的粘结指状物由于外部应力而分层或断裂，并避免对引线布局的干扰。

    Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package
    69.
    发明授权
    Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package 有权
    引线框半导体封装在支撑杆上具有拱形弯曲和用于封装的引线框架

    公开(公告)号：US07619307B1

    公开(公告)日：2009-11-17

    申请号：US12133898

    申请日：2008-06-05

    Applicant: Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

    Inventor： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495

    CPC classification number: H01L23/4951 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.

    Abstract translation: 揭示了一种基于引线框架的半导体封装和封装的引线框架。 半导体封装主要包括引线框架的包括一个或多个第一引线，一个或多个第二引线和布置在第一引线和第二引线之间的支撑杆的部分，还包括附接到第一引线，第二引线和 支撑杆，多根接合线和密封剂。 支撑杆具有从第一接合指和第二接合指突起的延伸部分，并且连接到密封剂的非引线侧，其中延伸部具有拱形弯曲部以吸收拉应力并阻止应力传递。 在沿着密封剂的非引线侧修整支撑杆时不会产生由支撑杆分层引起的裂纹。 期望地防止沿支撑杆的裂纹到芯片下方的芯片接合平面的水分渗透。

    SEMICONDUCTOR CHIP HAVING TSV (THROUGH SILICON VIA) AND STACKED ASSEMBLY INCLUDING THE CHIPS
    70.
    发明申请
    SEMICONDUCTOR CHIP HAVING TSV (THROUGH SILICON VIA) AND STACKED ASSEMBLY INCLUDING THE CHIPS 有权
    具有TSV（通过硅胶）的半导体芯片和包括芯片的堆叠组件

    公开(公告)号：US20090267194A1

    公开(公告)日：2009-10-29

    申请号：US12108903

    申请日：2008-04-24

    Applicant: Ming-Yao CHEN

    Inventor： Ming-Yao CHEN

    IPC: H01L23/488

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/08245 ,  H01L2224/80141 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

    Abstract: A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields.

    Abstract translation: 揭示了通过硅通孔（TSV）的半导体芯片和包括芯片的堆叠组件。 芯片具有分别设置在半导体衬底的两个相对表面上的多个第一和第二接合焊盘。 通孔垂直地穿过半导体衬底和第一和第二焊盘。 通过形成第一挤压环，第一接合焊盘具有位于第一挤压环和通孔之间的第一接触表面。 通过形成第二挤压环，第二接合焊盘具有位于第二挤压环的外侧并与第二挤压环相邻的第二接触表面，以环绕第二挤压环。 第二挤压环具有适合尺寸以适合第一挤出环。 因此，可以精确地对准多个半导体芯片，而不需要移位，从而有效地降低堆叠的组装高度，此外，首先通过垂直堆叠多个芯片，然后将导电材料填充到通孔中而不用电 由于导电材料溢出而导致相邻焊盘之间短路，以满足TSV的精细间距要求。 叠层组件的工艺流程可以通过更高的生产率得到简化。

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