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    Interconnect structure and method of making same
    63.
    发明授权
    Interconnect structure and method of making same 有权
    互连结构及其制作方法

    公开(公告)号：US09334572B2

    公开(公告)日：2016-05-10

    申请号：US14276360

    申请日：2014-05-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

    IPC: C23F4/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

    Abstract translation: 提供了互连结构及其制造方法。 更具体地，互连结构是无缺陷的封装互连结构。 该结构包括形成在没有帽材料的平坦化介电层的沟槽中的导电材料。 该结构还包括形成在导电材料上以防止迁移的盖材料。 形成结构的方法包括在电介质材料上选择性地沉积牺牲材料，并在介电材料的沟槽内的导电层上提供金属覆盖层。 该方法还包括用其上的任何不需要的沉积或有核的金属覆盖层去除牺牲材料。

    AUTOBAHN INTERCONNECT IN IC WITH MULTIPLE CONDUCTION LANES
    64.
    发明申请
    AUTOBAHN INTERCONNECT IN IC WITH MULTIPLE CONDUCTION LANES 有权
    多媒体IC中的AUTOBAHN INTERCONNECT

    公开(公告)号：US20160035674A1

    公开(公告)日：2016-02-04

    申请号：US14447499

    申请日：2014-07-30

    Applicant: The Board of Trustees of the Leland Stanford Junior University

    Inventor： Shoucheng Zhang ,  Jing Wang

    IPC: H01L23/532 ,  H01L23/528

    CPC classification number: H01L23/53204 ,  H01B1/16 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A topological insulator is grown on an IC wafer in a vacuum chamber as a thin film interconnect between two circuits in the IC communicating with each other. As the TI is being grown, magnetic doping of the various TI sub-layers is varied to create different edge states in the stack of sub-layers. The sub-edges conduct in parallel with virtually zero power dissipation. Conventional metal electrodes are formed on the IC wafer that electrically contact the four corners of the TI layer (including the side edges) to electrically connect a first circuit to a second circuit via the TI interconnect. The TI interconnect thus forms two independent conducting paths between the two circuits, with each path being formed of a plurality of sub-edges. This allows bi-direction communications without collisions. Since each electrode contacts many sub-edges in parallel, the overall contact resistance is extremely low.

    Abstract translation: 拓扑绝缘体在真空室中的IC晶片上生长，作为IC中的两个电路之间的薄膜互连，彼此通信。 随着TI正在种植，各种TI子层的磁性掺杂是变化的，以在子层叠中产生不同的边缘状态。 子边缘平行导通，功耗几乎为零。 传统的金属电极形成在与IC层（包括侧边缘）的四个角电接触的IC晶片上，以通过TI互连将第一电路电连接到第二电路。 因此，TI互连在两个电路之间形成两个独立的导电路径，每个路径由多个子边缘形成。 这允许双向通信而没有冲突。 由于每个电极平行接触多个子边缘，因此整体接触电阻极低。

    Method for forming voids of structure
    67.
    发明授权
    Method for forming voids of structure 有权
    形成结构空隙的方法

    公开(公告)号：US09159697B2

    公开(公告)日：2015-10-13

    申请号：US14219042

    申请日：2014-03-19

    Applicant: Wistron Corporation

    Inventor： Hui-Ying Chou ,  Lee-Chieh Kang

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L23/00 ,  H01L23/13

    CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L23/528 ,  H01L23/53204 ,  H05K3/0005 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

    Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.

    Abstract translation: 提供了一种形成对应于SMT部件的焊盘的空隙的方法。 该方法包括以下步骤：将一个或多个条件参数输入到搜索单元。 参考条件参数，搜索单元搜索所有的焊盘，以获得预选的焊盘组。 提供判断单元以确定预先选择的焊盘组中的每个焊盘是否满足预定的处理要求以生成要处理的焊盘组。 执行单元参照要处理的一组焊盘的角坐标来执行空隙形成步骤，以便在与焊盘的角部相对应的接触表面的部分处形成至少一个空隙。 在一个实施例中，相应地在接触表面处形成与被处理组的每个焊盘的各个角相关的四个空隙。

    Semiconductor device manufacturing method and semiconductor device
    69.
    发明授权
    Semiconductor device manufacturing method and semiconductor device 有权
    半导体器件制造方法和半导体器件

    公开(公告)号：US09093504B2

    公开(公告)日：2015-07-28

    申请号：US13788894

    申请日：2013-03-07

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Masakatsu Tsuchiaki

    IPC: H01L21/768 ,  H01L23/532 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L21/76889 ,  H01L21/76885 ,  H01L23/53204 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is manufactured by forming, on an insulating base material, a first support element having a side face that extends from a surface of the insulating base material, forming a coating of amorphous silicon on the side face of the first support element, filling an aperture disposed between the first support element and a second support element that extends from a surface of the insulating base material with an insulating film, planarizing the insulating film to expose an exposed portion of the coating and a surface of the first support element, and siliciding the amorphous silicon of the coating to form an interconnect.

    Abstract translation: 半导体器件通过在绝缘基材上形成具有从绝缘基材的表面延伸的侧面的第一支撑元件，在第一支撑元件的侧面上形成非晶硅的涂层，填充 设置在所述第一支撑元件和第二支撑元件之间的孔，所述第二支撑元件由绝缘基材的表面以绝缘膜延伸，平坦化所述绝缘膜以暴露所述涂层的暴露部分和所述第一支撑元件的表面，以及 硅化涂层的非晶硅以形成互连。

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