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公开(公告)号：US5125451A
公开(公告)日：1992-06-30
申请号：US679529
申请日：1991-04-02
Applicant: James A. Matthews
Inventor： James A. Matthews
IPC: F28F3/04 , F28F3/12 , H01L23/473
CPC classification number: F28F3/12 , H01L23/473 , F28D2021/0029 , F28F2260/02 , H01L2924/0002 , Y10T29/49366 , Y10T29/49368
Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.
Abstract translation: 适于冷却诸如半导体集成电路的发热装置的微型层流式热交换器包括多个薄板，层压在一起以形成块体。 每个板具有蚀刻到板的一个面中的微观凹陷部分和穿过板切割的一对孔，使得当形成块时，孔对准以形成一对冷却剂分配歧管。 在层压过程中，歧管通过由凹部形成的多个微细通道相连接。 通过这些通道的冷却液流动可实现除热。
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公开(公告)号：US3098106A
公开(公告)日：1963-07-16
申请号：US85759659
申请日：1959-12-07
Applicant: EXXON RESEARCH ENGINEERING CO
Inventor： ROGERS EDWARDS WILLIAM
CPC classification number: C10L1/04 , C07C5/10 , C07C2521/04 , C07C2523/42 , C07C2523/72 , C07C2523/755 , C07C2523/882 , C07C2527/049
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公开(公告)号：US10365926B2
公开(公告)日：2019-07-30
申请号：US15147811
申请日：2016-05-05
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/30 , G06F9/38 , G06F9/35 , G06F9/455 , G06F12/02 , G06F17/50 , H03M13/15 , H03M13/41 , G06F9/448 , G06F9/44 , G03F1/36
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
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公开(公告)号：US20190065149A1
公开(公告)日：2019-02-28
申请号：US16150224
申请日：2018-10-02
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
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公开(公告)号：US08269784B2
公开(公告)日：2012-09-18
申请号：US13354214
申请日：2012-01-19
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/30014 , G06F9/30007 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/34 , G06F9/3824 , G06F9/383 , G06F9/3885 , G06F12/0886
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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Patent Agency Ranking
公开(公告)号：US08117426B2
公开(公告)日：2012-02-14
申请号：US11878803
申请日：2007-07-27
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.
Abstract translation: 提出了一种可编程处理器的系统和装置，其包括执行单元，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行群组数据处理 响应于数据处理指令以不同方式重新布置数据元素的操作，所述执行单元还能够执行多个不同的组浮点和组整数运算，每个算术运算对存储在寄存器中的多个数据元素进行算术运算 该寄存器文件产生一个返回到该寄存器文件中的一个寄存器的连线结果，其中该连接结果包括多个单独的结果。
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77.发明授权公开(公告)号：US07987344B2
公开(公告)日：2011-07-26
申请号：US10757939
申请日：2004-01-16
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.
Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可配置为执行来自所述多个线程的多个指令流，其中每个指令流包括对分割字段中的多个数据元素进行操作的组指令， 至少有一个寄存器产生连带结果。
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公开(公告)号：US07948496B2
公开(公告)日：2011-05-24
申请号：US11982051
申请日：2007-10-31
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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79.发明授权Processor for executing switch and translate instructions requiring wide operands 有权用于执行切换和转换需要广泛操作数的指令的处理器公开(公告)号：US07932911B2
公开(公告)日：2011-04-26
申请号：US11982171
申请日：2007-10-31
Applicant: Craig Hansen , John Moussouris , Alexia Massalin
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F12/02 , G06F9/30007 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/383 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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80.发明授权公开(公告)号：US07653806B2
公开(公告)日：2010-01-26
申请号：US11842077
申请日：2007-10-29
Applicant: Craig Hansen , John Moussouris
Inventor： Craig Hansen , John Moussouris
IPC: G06F9/38
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.
Abstract translation: 提出了一种系统和装置，其涉及包括执行单元的可编程处理器，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行多个 不同的组浮点和组整数算术运算，每个算术运算在寄存器文件中的多个数据元素存储的寄存器上产生返回到寄存器文件中的寄存器的连接结果，其中，连接结果包括多个单独的结果 其中，所述执行单元能够执行响应于数据处理指令以不同方式重新布置数据元素的组数据处理操作。
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