公开(公告)号：US20240406163A1

公开(公告)日：2024-12-05

申请号：US18678831

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy ,  Maxime Mere ,  Frédéric Jouault

IPC: H04L9/40 ,  G06F21/10 ,  H04L9/32

Abstract: A method for life cycle management of a system-on-chip having functions includes multi-user ownership management listing owners of the functions in a directory, and allocating rights of a function over the life cycle of the system-on-chip, according to a configuration command including identifying the function, identifying a right of ownership or access to the function, and a signature of the owner of the function.

公开(公告)号：US20240405111A1

公开(公告)日：2024-12-05

申请号：US18204009

申请日：2023-05-31

Applicant: STMicroelectronics International N.V.

Inventor： Christophe MAURIAC ,  Laurent SIEGERT

IPC: H01L29/747

Abstract: A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.

公开(公告)号：US20240405098A1

公开(公告)日：2024-12-05

申请号：US18623604

申请日：2024-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

公开(公告)号：US20240404940A1

公开(公告)日：2024-12-05

申请号：US18678025

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Pascal CHEVALIER

IPC: H01L23/498 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735

Abstract: A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.

公开(公告)号：US20240404569A1

公开(公告)日：2024-12-05

申请号：US18675916

申请日：2024-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Riccardo ZURLA

IPC: G11C7/16 ,  G06F7/544 ,  G11C11/54 ,  G11C13/00

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.

公开(公告)号：US20240402743A1

公开(公告)日：2024-12-05

申请号：US18678767

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Helene ESCH ,  Jerome BOURGOIN ,  Eric FELTRIN

IPC: G05F1/575 ,  G05F1/573

Abstract: A voltage regulator has a first output is connected to a capacitive element. A current source is coupled between the first output and a first node receiving a power supply voltage. The current source delivers a first DC current in response to assertion of a first binary signal. A comparator asserts a second binary signal when a first voltage on the first output is lower than a set point voltage. A first circuit controls assertion of the first signal for a first fixed time period when the second binary signal is asserted.

公开(公告)号：US20240402358A1

公开(公告)日：2024-12-05

申请号：US18671027

申请日：2024-05-22

Applicant: STMicroelectronics International N.V.

Inventor： Jerome DURAND ,  Nicola Matteo PALELLA ,  Leonardo COLOMBO

IPC: G01S19/39 ,  G01S19/29 ,  G01S19/42 ,  G01S19/52 ,  H04W4/029

Abstract: A device includes global positioning circuitry, sensing circuitry, and processing circuitry. The global positioning circuitry, in operation, receives location-related data. The sensing circuitry, in operation, senses data related to the device. The processing circuitry, in operation, determines a motion state of the electronic system based on data sensed by the sensing circuitry, and selects a plurality of control parameters from one or more configuration matrixes based on the determined motion state. The plurality of control parameters includes a power-mode control parameter and a location-determination control parameter. The processing circuitry configures a power-mode of the device based on the power-mode control parameter, and determines a location characteristic of the device based on the received location-related data and the location-determination control parameter.

公开(公告)号：US20240396535A1

公开(公告)日：2024-11-28

申请号：US18666532

申请日：2024-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Rohit Kumar GUPTA

IPC: H03K3/037 ,  H03K3/012

Abstract: A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.

公开(公告)号：US20240393500A1

公开(公告)日：2024-11-28

申请号：US18202418

申请日：2023-05-26

Applicant: STMicroelectronics International N.V.

Inventor： Enrico Giuseppe CARNEMOLLA ,  James Peter Drummond DOWNING ,  Matteo FISSORE

IPC: G02B1/00 ,  G02B27/00 ,  G06F30/12

Abstract: A metasurface optic, designed for short-wave infrared (SWIR) range devices, is formed of one or more unit cells with a specific arrangement of truncated cone-shaped subwavelength nanostructures, tailored to achieve various optical functionalities. The one or more unit cells are formed from a design set selected from among multiple different design sets, each of the multiple different design sets featuring truncated cones having a unique combination of height (800 nm to 1100 nm), sidewall angle (91° to) 93°, and pitch (550 nm to 750 nm), with base radius values of the truncated cones within a given design set varying from 75 nm to 250 nm in 1 nm increments.

公开(公告)号：US20240385241A1

公开(公告)日：2024-11-21

申请号：US18199065

申请日：2023-05-18

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep JAIN ,  Pooja JAIN ,  Esha PAL

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185

Abstract: Test circuitry includes a scan-compressor receiving n scan-input bits from n input-pins and compressing those bits for distribution among z scan-chains, z being less than n. A scan-decompressor receives test response data from the scan-chains and decompresses the test response data, reconstructing n scan-output bits. An OCC generates a test-clock based on clock-bits received from a clock-chain, with the test-clock operating the scan-chains and the clock-chain. The clock-chain receives m clock-chain input bits from m of the input-pins, m being less than n, and provides the clock-bits to the OCC for generating the test-clock. The test circuitry performs tests on the IC. Each test is associated with the test-clock generated by the OCC based on a given set of clock-bits. Tests associated with the test-clock generated by the OCC based on the same given set of clock-bits are performed after a single loading of that same given set of clock-bits.