公开(公告)号：US20120261770A1

公开(公告)日：2012-10-18

申请号：US13086397

申请日：2011-04-14

Applicant: Kun-Hsien Lin ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chi-Mao Hsu ,  Chin-Fu Lin

Inventor： Kun-Hsien Lin ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L29/772

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7833

Abstract: A metal gate structure includes a high-K gate dielectric layer, an N-containing layer, a work function metal layer, and an N-trapping layer. The N-containing layer is positioned between the work function metal layer and the high-K gate dielectric layer. The N-trapping layer is positioned between the work function metal layer and the high-K gate dielectric layer, and the N-trapping layer contains no nitrogen or low-concentration nitrogen.

Abstract translation: 金属栅极结构包括高K栅极电介质层，N含量层，功函数金属层和N-捕获层。 N层位于功函数金属层和高K栅极电介质层之间。 N捕获层位于功函数金属层和高K栅介质层之间，N捕获层不含氮或低浓度氮。

公开(公告)号：US20120248507A1

公开(公告)日：2012-10-04

申请号：US13072795

申请日：2011-03-28

Applicant: Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Teng-Chun Tsai ,  Chin-Cheng Chien

Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Teng-Chun Tsai ,  Chin-Cheng Chien

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/66545

Abstract: A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).

Abstract translation: 金属栅极结构的制造方法包括提供具有形成在其上的至少第一金属氧化物层的基板，并将第一金属氧化物层的表面转移到第二金属氧化物层中。 第一金属氧化物层包括第一金属（M1）的金属氧化物（M1Ox），第二金属氧化物层包括第一金属的金属氧化物（（M1M2Oy））和第二金属（M2）。

公开(公告)号：US20110156188A1

公开(公告)日：2011-06-30

申请号：US12947970

申请日：2010-11-17

Applicant: Hsiu-Wen Tu ,  Chung-Hsien Hsin ,  Chun-Hua Chuang ,  Ren-Long Kuo ,  Chin-Fu Lin ,  Young-Houng Shiao

Inventor： Hsiu-Wen Tu ,  Chung-Hsien Hsin ,  Chun-Hua Chuang ,  Ren-Long Kuo ,  Chin-Fu Lin ,  Young-Houng Shiao

IPC: H01L31/0232

CPC classification number: H01L27/14618 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/1815 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

Abstract: An image sensor packaging structure with a low transmittance encapsulant is provided. The image sensor packaging structure includes a substrate, a chip, a transparent lid, and the low transmittance encapsulant. The chip is combined with the substrate. The transparent lid is adhered to the chip and cover above a sensitization area of the chip to form an air cavity. The low transmittance encapsulant is formed on the substrate and encapsulates the chip and the transparent lid so as to accomplish the package of the image sensor packaging structure. Due to the feature of prohibiting from light passing through the low transmittance encapsulant, the arrangement of the low transmittance encapsulant can avoid the light from outside interfere the image sensing effect of the image sensor. Therefore, the quality of the image sensing can be ensured.

Abstract translation: 提供了具有低透射率密封剂的图像传感器封装结构。 图像传感器封装结构包括基板，芯片，透明盖和低透光性密封剂。 芯片与基板结合。 透明盖子粘贴在芯片上并覆盖在芯片的敏化区域上方形成一个空气腔。 低透光性密封剂形成在基板上并封装芯片和透明盖，从而实现图像传感器封装结构的封装。 由于禁止光通过低透射率密封剂的特征，低透射率密封剂的布置可以避免来自外部的光干扰图像传感器的图像感测效果。 因此，可以确保图像感测的质量。

公开(公告)号：US20110156187A1

公开(公告)日：2011-06-30

申请号：US12947210

申请日：2010-11-16

Applicant: Hsiu-Wen Tu ,  Chung-Hsien Hsin ,  Chun-Hua Chuang ,  Ren-Long Kuo ,  Chin-Fu Lin ,  Young-Houng Shiao

Inventor： Hsiu-Wen Tu ,  Chung-Hsien Hsin ,  Chun-Hua Chuang ,  Ren-Long Kuo ,  Chin-Fu Lin ,  Young-Houng Shiao

IPC: H01L31/0232

CPC classification number: H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/4554

Abstract: An image sensor packaging structure with a predetermined focal length is provided. The image sensor packaging structure includes a substrate, a chip, an optical assembly, and an encapsulation compound. The chip has a sensitization area and is coupled to the substrate. Conductive contacts on the substrate are electrically connected with conductive contacts around the sensitization area. The optical assembly has the predetermined focal length and is disposed above the chip so as to form an air cavity between the optical assembly and the sensitization area of the chip. The encapsulation compound is formed on the substrate to surround the chip and the optical assembly. With the above stated structure, not only can the focus adjusting procedure be dispensed with, but also the image sensor packaging structure can be manufactured by a molding or dispensing process.

Abstract translation: 提供具有预定焦距的图像传感器封装结构。 图像传感器封装结构包括基板，芯片，光学组件和封装化合物。 该芯片具有敏化区域并且耦合到该基板。 基板上的导电触点与敏化区周围的导电触点电连接。 光学组件具有预定的焦距并且设置在芯片上方，以在光学组件和芯片的敏化区域之间形成空气腔。 封装化合物形成在衬底上以包围芯片和光学组件。 利用上述结构，不仅可以省略聚焦调整过程，而且可以通过模制或分配过程来制造图像传感器封装结构。

公开(公告)号：US08847146B2

公开(公告)日：2014-09-30

申请号：US12579493

申请日：2009-10-15

Applicant: Hsiu-Wen Tu ,  Ren-Long Kuo ,  Young-Houng Shiao ,  Tsao-Pin Chen ,  Mon-Nan Ho ,  Chih-Cheng Hsu ,  Chin-Fu Lin ,  Chung-Hsien Hsin

Inventor： Hsiu-Wen Tu ,  Ren-Long Kuo ,  Young-Houng Shiao ,  Tsao-Pin Chen ,  Mon-Nan Ho ,  Chih-Cheng Hsu ,  Chin-Fu Lin ,  Chung-Hsien Hsin

IPC: H01J5/02 ,  H01L31/0203 ,  H01L27/146 ,  H01L23/10 ,  H01L23/04

CPC classification number: H01L27/14618 ,  H01L23/04 ,  H01L23/10 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention discloses an image sensor package structure. The image sensor package structure includes a substrate, a chip, a transparent lid, a first casing and a package material. The transparent lid covers a sensitization area of the chip and it also adheres to the chip which is deposed on the substrate. The first casing, which adheres to the transparent lid, forms an opening so that light can pass through the opening and the transparent lid to enter into the sensitization area. The package material covers around the chip and the transparent lid and fills between the substrate and the first casing. Because of the arrangement of adhesive layers placed between the first casing and the transparent lid and between the transparent lid and the chip, the blockage area from moisture is elongated. Therefore, the reliability of the image sensor package structure can be enhanced.

Abstract translation: 本发明公开了一种图像传感器封装结构。 图像传感器封装结构包括基板，芯片，透明盖，第一壳体和封装材料。 透明盖子覆盖了芯片的敏化区域，并且还粘附在衬底上的芯片上。 附着在透明盖上的第一壳体形成开口，使得光线可以穿过开口和透明盖子进入致敏区域。 封装材料围绕芯片和透明盖子覆盖并填充在基板和第一壳体之间。 由于布置在第一壳体和透明盖之间以及透明盖和芯片之间的粘合剂层的布置，所以来自湿气的阻塞区域被拉长。 因此，可以提高图像传感器封装结构的可靠性。

公开(公告)号：US08841733B2

公开(公告)日：2014-09-23

申请号：US13109599

申请日：2011-05-17

Applicant: Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供了一种衬底，其中在衬底上形成有沟槽的第一电介质层，在沟槽的两侧在衬底中形成源极/漏极区，并且在沟槽中的衬底上形成第二电介质层 。 进行第一物理气相沉积工艺以在沟槽中形成含Ti金属层。 进行第二物理气相沉积工艺以在沟槽中的含Ti金属层上形成Al层。 进行热处理以使含Ti金属层和Al层退火以形成功函数金属层。 形成金属层以填充沟槽。

公开(公告)号：US08836049B2

公开(公告)日：2014-09-16

申请号：US13495009

申请日：2012-06-13

Applicant: Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC: H01L29/94 ,  H01L29/76

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 此外，还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US08822284B2

公开(公告)日：2014-09-02

申请号：US13370231

申请日：2012-02-09

Applicant: Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/318 ,  H01L21/314

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

Abstract translation: 描述了制造FinFET的方法。 图案化半导体衬底以形成奇数鳍片。 间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。 然后在间隔件之间的基板上均匀形成翅片。 还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

公开(公告)号：US20140054654A1

公开(公告)日：2014-02-27

申请号：US13591226

申请日：2012-08-22

Applicant: Ya-Hsueh Hsieh ,  Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Chin-Fu Lin

Inventor： Ya-Hsueh Hsieh ,  Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor.

Abstract translation: MOS晶体管包括在衬底上的栅极结构，并且栅极结构包括从底部到顶部的润湿层，过渡层和低电阻率材料，其中过渡层具有功函数层的性质，并且栅极结构 没有任何功能层。 此外，本发明提供一种形成所述MOS晶体管的MOS晶体管工艺。

公开(公告)号：US08647941B2

公开(公告)日：2014-02-11

申请号：US13211319

申请日：2011-08-17

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/8238

CPC classification number: H01L29/7846 ,  H01L21/76283 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.

Abstract translation: 形成半导体器件的方法包括以下步骤。 提供具有第一应变硅层的半导体衬底。 然后，形成诸如浅沟槽隔离（STI）的绝缘区域，其中绝缘区域的深度基本上大于第一应变硅层的深度。 随后，去除第一应变硅层，形成第二应变硅层以代替第一应变硅层。