公开(公告)号：US20040094778A1

公开(公告)日：2004-05-20

申请号：US10694780

申请日：2003-10-29

Applicant: Renesas Technology Corp.

Inventor： Tsukasa Ooishi

IPC: H01L027/10

CPC classification number: G11C11/16 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.

公开(公告)号：US20040094206A1

公开(公告)日：2004-05-20

申请号：US10682076

申请日：2003-10-10

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Shoji Ishida

IPC: G05D007/06

CPC classification number: G05D7/0658 ,  Y10T137/7759 ,  Y10T137/7761 ,  Y10T137/87917

Abstract: An opening/closing of a plurality of valves are controlled so that a plurality of gases flow into a chamber in an operation of a semiconductor manufacturing apparatus, and the opening/closing of the plurality of valves are controlled so that a gas A flows into mass flowmeters in an inspection of a mass flow controller MFC 2null. Therefore, the inspection can be achieved while maintaining the connection of mass flow controller MFC 2null to the semiconductor manufacturing apparatus.

Abstract translation: 控制多个阀的打开/关闭，使得多个气体在半导体制造装置的操作中流入室中，并且控制多个阀的打开/关闭，使得气体A流入质量 流量计检查质量流量控制器MFC 2'。 因此，可以在保持质量流量控制器MFC 2'与半导体制造装置的连接的同时进行检查。

公开(公告)号：US20040087298A1

公开(公告)日：2004-05-06

申请号：US10682928

申请日：2003-10-14

Applicant: Renesas Technology Corp.

Inventor： Taizo Yamawaki ,  Satoshi Tanaka

IPC: H04B001/26 ,  H04B015/00

CPC classification number: H04B1/406

Abstract: The present invention relates to miniaturization of a local signal generation circuit to supply signals to a frequency converter in communication terminals such as a transmitter, a receiver, a transmitter-receiver, and the like that use one or more frequency bands. The local signal generation circuit comprises first and second oscillators capable of changing output frequencies and a multiplication means for multiplying input signals and generates local signals. The multiplication means selectively generates a signal of frequency corresponding to a sum or a difference between an output signal from the first oscillator and an output signal from the second oscillator.

Abstract translation: 本发明涉及本地信号发生电路的小型化，以向诸如使用一个或多个频带的发射机，接收机，发射机 - 接收机等的通信终端中的频率转换器提供信号。 本地信号发生电路包括能够改变输出频率的第一和第二振荡器以及用于乘以输入信号并产生本地信号的乘法装置。 乘法装置选择性地产生对应于来自第一振荡器的输出信号和来自第二振荡器的输出信号之间的和或差的频率的信号。

公开(公告)号：US20040076072A1

公开(公告)日：2004-04-22

申请号：US10682479

申请日：2003-10-10

Applicant: Renesas Technology Corp.

Inventor： Tsuyoshi Arigane ,  Takashi Kobayashi ,  Yoshitaka Sasago

IPC: G11C008/02

CPC classification number: G11C16/0408 ,  H01L27/115

Abstract: A nonvolatile semiconductor memory device improved with integration degree, in which the gate of the selection transistors is separated on each of active regions, first and second selection transistors are arranged in two stages in the direction of the global bit line, the gates for the selection transistors in each stage are disposed on every other active regions, contact holes are formed in mirror asymmetry with respect to line B-B in the connection portion for the active regions, the gate is connected through the contact hole to the wiring, the adjacent active regions are connected entirely in one selection transistor portion and connected in an H-shape for adjacent two active regions in another selection transistor portion, and the contact hole is formed in the connection -portion and connected when the global bit line, whereby the pitch for the selection transistor portion can be decreased in the direction of the global bit line.

Abstract translation: 一种以积分度改善的非易失性半导体存储器件，其中选择晶体管的栅极在每个有源区域上分离，第一和第二选择晶体管沿全局位线的方向分两级布置，用于选择栅极 每个级中的晶体管设置在每个其他有源区上，在有源区的连接部分中，相对于线BB在接触孔中形成接触孔，栅极通过接触孔连接到布线，相邻的有源区是 完全在一个选择晶体管部分连接并连接在另一个选择晶体管部分中的相邻两个有源区域的H形中，并且接触孔形成在连接部分中并且在全局位线处连接，由此用于选择的间距 晶体管部分可以在全局位线的方向上减小。

公开(公告)号：US20040068590A1

公开(公告)日：2004-04-08

申请号：US10665558

申请日：2003-09-22

Applicant: Renesas Technology Corp. ,  Renesas Northern Japan Semiconductor, Inc. ,  Hitachi Device Engineering Co., Ltd.

Inventor： Tatsuo Nishino ,  Mamoru Wakabayashi ,  Toru Ichien

IPC: G06F003/00

CPC classification number: G06F13/385 ,  G06F2213/0038

Abstract: In this data processor, the semiconductor chip comprises a central processing unit, an interface controller, and a bus controller. The interface controller further includes an interface control unit, a FIFO unit, and a transfer control unit. The interface control unit outputs the data of the FIFO unit to the external side of the semiconductor chip and inputs the data inputted from the external side of the semiconductor chip to the FIFO unit. The transfer control unit performs the control to transfer the data stored in the FIFO unit by designating the transfer destination address and the control to input the data to the FIFO unit by designating the transfer source address. The control by the data transfer control device is not included in the transfer control by the transfer control device. Accordingly, the time required for the data transfer between the on-chip interface controller and the external side can be curtailed.

Abstract translation: 在该数据处理器中，半导体芯片包括中央处理单元，接口控制器和总线控制器。 接口控制器还包括接口控制单元，FIFO单元和传送控制单元。 接口控制单元将FIFO单元的数据输出到半导体芯片的外部，并将从半导体芯片的外部侧输入的数据输入到FIFO单元。 传送控制单元通过指定传送目的地地址和控制，通过指定传送源地址来执行控制以传送存储在FIFO单元中的数据以将数据输入到FIFO单元。 数据传送控制装置的控制不包括在传送控制装置的传送控制中。 因此，可以减少片上接口控制器和外部侧之间的数据传输所需的时间。

公开(公告)号：US20040029369A1

公开(公告)日：2004-02-12

申请号：US10614789

申请日：2003-07-09

Applicant: Renesas Technology Corp.

Inventor： Kazuyuki Tokorozuki ,  Tetsuji Yokouchi ,  Yoshiyuki Miyamoto ,  Koji Yamamoto

IPC: H01L021/22

CPC classification number: G03F7/70558

Abstract: An average value of dimensions of resist patterns formed each time exposure processing is effected on semiconductor substrates of a predetermined number of lots, is compared with a target dimension. When a drift between each of the dimensions of the formed resist patterns and the target dimension is larger than a first value, exposure energy is corrected with a relatively large correction value null1. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the first value and larger than a second value, exposure energy is corrected with a relatively small correction value null2. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the second value, no exposure energy is corrected. Exposure processing is effected on a semiconductor substrate of the next lot by using the calculated exposure energy.

公开(公告)号：US20030231527A1

公开(公告)日：2003-12-18

申请号：US10445009

申请日：2003-05-27

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yasunobu Nakase ,  Koji Nii

IPC: G11C007/08

CPC classification number: G11C7/227 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/24 ,  G11C2207/2281

Abstract: Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

Abstract translation: 虚拟单元被分成多个划分的虚拟列，并且分割的虚拟位线对应于分割的虚拟列排列。 这些分开的虚拟位线设置有虚拟读出放大器，其驱动感测控制线传输感测使能信号来激活读出放大器。 可以实现读出放大器的更快的激活定时。

公开(公告)号：US20040263366A1

公开(公告)日：2004-12-30

申请号：US10878250

申请日：2004-06-29

Applicant: Renesas Technology Corp.

Inventor： Naoki Yada ,  Yasuyuki Saito

IPC: H03M001/06

CPC classification number: H03M1/1023 ,  H03M1/46 ,  H03M1/682 ,  H03M1/765

Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.

Abstract translation: 一种包括能够将通过外部端子接收的模拟信号转换为数字信号的A / D转换器的半导体集成电路。 A / D转换器包括：用于产生参考电压的梯形电阻器; 一组第一运算放大器，每个接收梯形电阻器的输出电压; 一组第一开关，每个能够使第一运算放大器的相应一个输入端子和输出端子短路，从而允许相应的第一运算放大器的偏移校正; 以及用于将每个第一运算放大器的输出电压与模拟信号进行比较的比较器电路。 A / D转换器可以减少梯形电阻器的电流输出，并加快采样电容器的充电和放电。

公开(公告)号：US20040263243A1

公开(公告)日：2004-12-30

申请号：US10870956

申请日：2004-06-21

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS DEVICE DESIGN CORP.

Inventor： Katsumi Miyazaki

IPC: H03F001/02

CPC classification number: H03F3/45968 ,  H03F1/02 ,  H03F3/211

Abstract: A BTL amplifier has a resistance element connected to an output reference voltage input terminal of an inverting amplifier. For offset compensation of the BTL amplifier, a variable current source controller controls an input switching circuit to cause application of compensation input voltages sent from an internal reference voltage source to a first input terminal and a second input terminal. The variable current source controller also controls a variable current source in response to an output signal from a comparator to minimize an output offset voltage, whereby a current flowing through the resistance element is adjusted to control the voltage at the output reference voltage input terminal.

Abstract translation: BTL放大器具有连接到反相放大器的输出参考电压输入端的电阻元件。 对于BTL放大器的偏移补偿，可变电流源控制器控制输入开关电路，以将从内部参考电压源发送的补偿输入电压施加到第一输入端和第二输入端。 可变电流源控制器还响应于来自比较器的输出信号来控制可变电流源，以最小化输出偏移电压，由此调节流过电阻元件的电流以控制输出参考电压输入端子处的电压。

公开(公告)号：US20040262747A1

公开(公告)日：2004-12-30

申请号：US10732521

申请日：2003-12-11

Applicant: Renesas Technology Corp.

Inventor： Masahide Kiritani

IPC: H01L023/34

CPC classification number: G01R31/318513 ,  G01R31/2818 ,  G01R31/318505 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A selector has the first input terminal to which a test signal is given, the second input terminal connected to an output terminal of the first internal logic circuit, and an output terminal connected via a wiring to an input terminal of the second internal logic circuit. Another selector has an input terminal connected to the wiring, another input terminal connected to an output terminal of the second internal logic circuit, and an output terminal connected via another wiring to a signal input terminal of the second internal logic circuit. Each of the selectors selectively outputs a signal given to its first input terminal or a signal given to its second input terminal B based on a test mode signal.

Abstract translation: 选择器具有给定测试信号的第一输入端子，连接到第一内部逻辑电路的输出端子的第二输入端子和经由布线连接到第二内部逻辑电路的输入端子的输出端子。 另一个选择器具有连接到布线的输入端子，连接到第二内部逻辑电路的输出端子的另一输入端子以及经由另一布线连接到第二内部逻辑电路的信号输入端子的输出端子。 每个选择器基于测试模式信号选择性地输出给予其第一输入端的信号或给予其第二输入端B的信号。