公开(公告)号：US11694739B2

公开(公告)日：2023-07-04

申请号：US17564575

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

CPC classification number: G11C11/40615

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US20230004459A1

公开(公告)日：2023-01-05

申请号：US17864804

申请日：2022-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/14

Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

公开(公告)号：US20220091921A1

公开(公告)日：2022-03-24

申请号：US17544074

申请日：2021-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  H03M13/29 ,  G06F11/10

Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.

公开(公告)号：US20220028450A1

公开(公告)日：2022-01-27

申请号：US16938855

申请日：2020-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C11/406 ,  G06F1/3203 ,  G06F9/4401

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US11200106B2

公开(公告)日：2021-12-14

申请号：US16705913

申请日：2019-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  H03M13/29 ,  G06F11/10

Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.

公开(公告)号：US11194382B2

公开(公告)日：2021-12-07

申请号：US16162215

申请日：2018-10-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kedarnath Balakrishnan

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3296 ,  G11C7/22 ,  G06F1/3234 ,  G06F13/16 ,  G06F1/3228 ,  G06F1/3225 ,  G06F11/34

Abstract: A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.

公开(公告)号：US20210200618A1

公开(公告)日：2021-07-01

申请号：US16730113

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F11/16 ,  G06F11/30 ,  G06F3/06

Abstract: A memory controller includes a command queue, a memory interface queue, and a non-volatile error reporting circuit. The command queue receives memory access commands including volatile reads, volatile writes, non-volatile reads, and non-volatile writes, and an output. The memory interface queue has an input coupled to the output of the command queue, and an output for coupling to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

公开(公告)号：US20210073152A1

公开(公告)日：2021-03-11

申请号：US17100254

申请日：2020-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

公开(公告)号：US10403333B2

公开(公告)日：2019-09-03

申请号：US15211887

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

IPC: G11C7/10 ,  G06F12/1018 ,  G11C11/408

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

公开(公告)号：US10402120B2

公开(公告)日：2019-09-03

申请号：US15272626

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G06F3/06 ,  G06F13/16

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.