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公开(公告)号：US20160378667A1
公开(公告)日：2016-12-29
申请号：US14747933
申请日：2015-06-23
Applicant: Advanced Micro Devices, Inc.
Inventor： David Andrew Roberts , Mitesh R. Meswani , Sergey Blagodurov , Dmitri Yudanov , Indrani Paul
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F2212/6024
Abstract: A processor employs multiple prefetchers at a processor to identify patterns in memory accesses to different memory modules. The memory accesses can include transfers between the memory modules, and the prefetchers can prefetch data directly from one memory module to another based on patterns in the transfers. This allows the processor to efficiently organize data at the memory modules without direct intervention by software or by a processor core, thereby improving processing efficiency.
Abstract translation: 处理器在处理器中使用多个预取器来识别对不同存储器模块的存储器访问中的模式。 存储器访问可以包括存储器模块之间的传输，并且预取器可以基于传输中的模式将数据直接从一个存储器模块预取到另一个。 这允许处理器在存储器模块内有效地组织数据，而无需软件或处理器核心的直接干预，从而提高处理效率。
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72.发明授权公开(公告)号：US12236109B2
公开(公告)日：2025-02-25
申请号：US18201696
申请日：2023-05-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Pratik Mishra , Sergey Blagodurov , Atul Kumar Sujayendra Sandur
Abstract: A cloud computing system includes cloud orchestrator circuitry and fabric manager circuitry. The cloud orchestrator circuitry receives an input application and determines a task graph, a data graph, and a function popularity heap parameter for the input application. The task graph comprises an indication of function interdependency of functions of the input application, the data graph comprises an indication of data interdependency of the functions, and the function popularity heap parameter corresponds to a re-usability index for the functions. The fabric manager circuitry allocate a first programmable integrated circuit (IC) device to perform a first function of the input application based on the task graph, the data graph, and the function popularity heap parameter.
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73.发明授权公开(公告)号：US12190174B2
公开(公告)日：2025-01-07
申请号：US16425881
申请日：2019-05-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexandru Dutu , Sergey Blagodurov , Anthony T. Gutierrez , Matthew D. Sinclair , David A. Wood , Bradford M. Beckmann
Abstract: A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait instruction is part of a mutual exclusion synchronization primitive and is detected by determining that there is a low number of updates to the condition variable prior to detecting that the condition has been met. In a high contention scenario, the workgroup scheduler wakes up one workgroup and schedules another workgroup to be woken up at a time in the future. In a non-contention scenario, more than one workgroup can be woken up at the same time.
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74.发明公开公开(公告)号：US20240333519A1
公开(公告)日：2024-10-03
申请号：US18194394
申请日：2023-03-31
Applicant: Advanced Micro Devices, Inc.
Inventor： SeyedMohammad SeyedzadehDelcheh , Sergey Blagodurov , Donald Matthews, Jr. , Srilatha Manne
IPC: H04L9/32
CPC classification number: H04L9/3242
Abstract: The disclosed computing device can include super flow control unit (flit) generation circuitry configured to generate a super flit containing two or more flits having two or more requests embedded therein, wherein the two or more requests have the same destination node identifiers and the super flit has a variable size based on a flit size and a number of existing requests in a source node that target a same destination node. The device can additionally include authentication circuitry configured to append a message authentication code to a last flit of the super flit. The device can also include communication circuitry configured to send the super flit to a network switch configured to route the super flit to a destination node corresponding to the same destination node identifiers. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US20240319911A1
公开(公告)日：2024-09-26
申请号：US18731089
申请日：2024-05-31
Applicant: Advanced Micro Devices, Inc.
IPC: G06F3/06 , G06F9/50 , G06F12/0802
CPC classification number: G06F3/0655 , G06F3/0602 , G06F3/065 , G06F3/0653 , G06F9/5027 , G06F12/0802 , G06F2212/60
Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.
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Patent Agency Ranking
公开(公告)号：US12066965B2
公开(公告)日：2024-08-20
申请号：US16863149
申请日：2020-04-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： SeyedMohammad Seyedzadehdelcheh , Steven Raasch , Sergey Blagodurov
CPC classification number: G06F13/4027 , G06F13/4282 , H03M7/30 , H03M9/00
Abstract: Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.
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公开(公告)号：US12019566B2
公开(公告)日：2024-06-25
申请号：US16938364
申请日：2020-07-24
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sergey Blagodurov , Johnathan Alsop , Jagadish B. Kotra , Marko Scrbak , Ganesh Dasika
IPC: G06F13/16 , G06F9/30 , H04L45/122
CPC classification number: G06F13/1642 , G06F9/3004 , G06F9/30098 , G06F13/1663 , H04L45/122
Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.
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公开(公告)号：US11934331B2
公开(公告)日：2024-03-19
申请号：US16588612
申请日：2019-09-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Antonio Maria Franques Garcia
CPC classification number: G06F13/4027 , H04L12/46 , H04L45/02 , H04L47/28 , H04W28/0221 , H04W40/10 , H04W72/30
Abstract: Systems, apparatuses, and methods for dynamically selecting between wired and wireless interconnects for sending packets are disclosed. A system includes at least a hybrid communication engine and a plurality of interconnects for connecting to various end-points. The communication engine dynamically discovers and utilizes the best interconnect technology available in between given end-points. The communication engine dynamically chooses the physical interconnect that is best suited at any given time to send data from one source to one or multiple destinations. This communication can be either on-chip or across nodes. The communication engine makes a decision based on a set of predetermined parameters that can be re-adjusted by the application layer, such as latency of the transmission, message data size, physical distance from source to destination, the energy cost, and the current congestion on the alternative interconnects.
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公开(公告)号：US11914517B2
公开(公告)日：2024-02-27
申请号：US17094989
申请日：2020-11-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Marko Scrbak , Brandon K. Potter
IPC: G06F12/08 , G06F12/0877 , G06F12/0815
CPC classification number: G06F12/0877 , G06F12/0815 , G06F2212/621
Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.
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公开(公告)号：US11868778B2
公开(公告)日：2024-01-09
申请号：US16937189
申请日：2020-07-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Ganesh Dasika , Sergey Blagodurov , Seyedmohammad Seyedzadehdelcheh
CPC classification number: G06F9/342 , G06F9/30036 , G06F9/30101 , G06F9/30167 , G06F13/1657
Abstract: Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.
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