公开(公告)号：US09110671B2

公开(公告)日：2015-08-18

申请号：US13724599

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L Bircher ,  Mahdu S. S. Govindan ,  Michael J Schulte ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

公开(公告)号：US20150186160A1

公开(公告)日：2015-07-02

申请号：US14146588

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne

IPC: G06F9/445 ,  G06F11/34 ,  G06F12/08

CPC classification number: G06F11/3423 ,  G06F1/3243 ,  G06F11/3452 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/601 ,  Y02D10/152 ,  Y02D10/34 ,  Y02D50/20

Abstract: Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. Some embodiments configure a first component in a processing system based on a predicted duration of an active state of a second component of the processing system. The predicted duration is predicted based on one or more previous durations of an active state of the second component.

Abstract translation: 可以基于组件的活动状态的一个或多个先前持续时间来预测处理系统的组件的主动性能状态的持续时间。 可以基于组件的活动状态的预测持续时间来配置处理系统中的一个或多个实体，例如处理器核心或高速缓存。 一些实施例基于处理系统的第二组件的活动状态的预测持续时间来配置处理系统中的第一组件。 基于第二组件的活动状态的一个或多个先前持续时间预测预测持续时间。

公开(公告)号：US20150067266A1

公开(公告)日：2015-03-05

申请号：US14011616

申请日：2013-08-27

Applicant: Advanced Micro Devices, Inc

Inventor： Syed Ali Jafri ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/12

CPC classification number: G06F12/127 ,  G06F12/0804 ,  G06F12/123 ,  Y02D10/13

Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.

Abstract translation: 一级高速缓冲存储器从更高级别的缓存存储器接收修改的数据。 识别具有与修改的数据相关联的索引的一组高速缓存行。 修改后的数据被存储在高速缓存行中，其具有在修改数据被存储之前至少与驱逐优先级一样高的驱逐优先级，该缓存优先级在未修改的高速缓存行中具有最高驱逐优先级的未修改高速缓存行 组。

公开(公告)号：US20150039833A1

公开(公告)日：2015-02-05

申请号：US13957105

申请日：2013-08-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai K. Chang ,  Yasuko Eckert ,  Gabriel H. Loh ,  Lisa R. Hsu

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0848 ,  G06F12/122 ,  Y02D10/13

Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.

Abstract translation: 一种用于在高速缓冲存储器中有效地降低存储器的电力以降低功耗的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，每个存储体包括多个缓存集。 响应于对高速缓存阵列中的多个存储体的第一存储体断电的请求，高速缓存控制器在第一存储体中选择给定类型的高速缓存行，并且确定所选高速缓存行的各个参考位置是否超过 阈。 如果超过阈值，则将所选择的高速缓存行迁移到高速缓存阵列中的第二组。 如果不超过阈值，则将所选的高速缓存行写回低级存储器。

公开(公告)号：US20140297961A1

公开(公告)日：2014-10-02

申请号：US13854724

申请日：2013-04-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna Thottethodi ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0893

Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.

Abstract translation: 缓存存储器接收执行写入操作的请求。 请求指定一个地址。 首先确定高速缓冲存储器不包括与该地址对应的高速缓存行。 第二个确定是地址在堆栈指针的先前值和堆栈指针的当前值之间。 第三个确定写入历史指示符被设置为指定值。 响应于第一，第二和第三确定，在高速缓冲存储器中执行写入操作，而不等待与要执行的地址相对应的高速缓存填充。

公开(公告)号：US20140181412A1

公开(公告)日：2014-06-26

申请号：US13725011

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh ,  James M. O'Connor ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F12/0848

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括缓存和用于存储器请求的一个或多个源。 响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。 控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。 此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。 第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

公开(公告)号：US20140143497A1

公开(公告)日：2014-05-22

申请号：US13887196

申请日：2013-05-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1036 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/6032 ,  G06F2212/683 ,  G06F2212/684 ,  Y02B60/1225 ,  Y02D10/13

Abstract: A processor system presented here has a plurality of execution cores and a plurality of stack caches, wherein each of the stack caches is associated with a different one of the execution cores. A method of managing stack data for the processor system is presented here. The method maintains a stack cache manager for the plurality of execution cores. The stack cache manager includes entries for stack data accessed by the plurality of execution cores. The method processes, for a requesting execution core of the plurality of execution cores, a virtual address for requested stack data. The method continues by accessing the stack cache manager to search for an entry of the stack cache manager that includes the virtual address for requested stack data, and using information in the entry to retrieve the requested stack data.

Abstract translation: 这里呈现的处理器系统具有多个执行内核和多个堆栈高速缓存，其中每个堆栈高速缓存与不同的执行核心相关联。 此处介绍了处理器系统的堆栈数据管理方法。 该方法维护多个执行核心的堆栈高速缓存管理器。 堆栈缓存管理器包括由多个执行核心访问的堆栈数据的条目。 该方法对于多个执行核心的请求执行核心处理所请求的堆栈数据的虚拟地址。 该方法通过访问堆栈高速缓存管理器来继续搜索包括所请求的堆栈数据的虚拟地址的堆栈高速缓存管理器的条目，并使用条目中的信息来检索所请求的堆栈数据。

公开(公告)号：US12204774B2

公开(公告)日：2025-01-21

申请号：US17986623

申请日：2022-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru Dutu ,  Nuwan Jayasena ,  Yasuko Eckert ,  Niti Madan ,  Sooraj Puthoor

IPC: G06F3/06

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

公开(公告)号：US12079145B2

公开(公告)日：2024-09-03

申请号：US18103240

申请日：2023-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max Ruttenberg ,  Vendula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Anthony Gutierrez ,  Mark H. Oskin

IPC: G06F13/16 ,  G11C11/4076

CPC classification number: G06F13/1668 ,  G11C11/4076

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

公开(公告)号：US12033714B2

公开(公告)日：2024-07-09

申请号：US17224603

申请日：2021-04-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Yasuko Eckert

IPC: G11C5/02 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888

CPC classification number: G11C5/025 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0815 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/254 ,  G06F2212/502

Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.