公开(公告)号：US20180136569A1

公开(公告)日：2018-05-17

申请号：US15811341

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Mangesh BANGAR ,  Srinivas D. NEMANI ,  Steve G. GHANAYEM ,  Ellie Y. YIEH

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.

公开(公告)号：US20170287752A1

公开(公告)日：2017-10-05

申请号：US15445303

申请日：2017-02-28

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Mehdi VAEZ-IRAVANI ,  Todd EGAN ,  Mangesh BANGAR ,  Concetta RICCOBENE ,  Abdul Aziz KHAJA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Sean S. KANG

IPC: H01L21/67 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/67259 ,  H01L21/265 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/67288 ,  H01L22/20

Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.

公开(公告)号：US20170154776A1

公开(公告)日：2017-06-01

申请号：US15432368

申请日：2017-02-14

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

公开(公告)号：US20170092502A1

公开(公告)日：2017-03-30

申请号：US15240410

申请日：2016-08-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Ellie Y. YIEH ,  Mehul B. NAIK ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/28518 ,  C23C16/42 ,  C23C16/4418 ,  C23C16/511 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/28556 ,  H01L21/324 ,  H01L21/76864 ,  H01L21/76885 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271

Abstract: Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.

公开(公告)号：US20170053797A1

公开(公告)日：2017-02-23

申请号：US15346306

申请日：2016-11-08

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Ludovic GODET ,  Yin FAN

IPC: H01L21/02 ,  H01L29/66 ,  H01J37/32 ,  H01L21/3115

CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

Abstract translation: 提供了使用用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施方案中，在衬底上形成具有期望材料的结构的方法包括在形成在衬底上的结构的圆周上形成图案化的自组装单层，其中所述图案化的自组装单层包括在自身中形成的处理层 并且执行原子层沉积工艺，以从图案化的自组装单层形成主要在自组装单层上的材料层。

公开(公告)号：US20160293438A1

公开(公告)日：2016-10-06

申请号：US15080117

申请日：2016-03-24

Applicant: Applied Materials, Inc.

Inventor： Qingjun ZHOU ,  Jungmin KO ,  Tom CHOI ,  Sean KANG ,  Jeremiah PENDER ,  Srinivas D. NEMANI ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

公开(公告)号：US20160194758A1

公开(公告)日：2016-07-07

申请号：US14635589

申请日：2015-03-02

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Erica CHEN ,  Ludovic GODET ,  Jun XUE ,  Ellie Y. YIEH

IPC: C23C16/56 ,  C23C16/32 ,  C23C14/48 ,  C23C16/36 ,  C23C16/40 ,  C23C16/30 ,  C23C16/34

CPC classification number: C23C16/56 ,  C23C16/045 ,  C23C16/401

Abstract: Embodiments described herein relate to methods for forming flowable chemical vapor deposition (FCVD) films suitable for high aspect ratio gap fill applications. Various process flows described include ion implantation processes utilized to treat a deposited FCVD film to improve dielectric film density and material composition. Ion implantation processes, curing processes, and annealing processes may be utilized in various sequence combinations to form dielectric films having improved densities at temperatures within the thermal budget of device materials. Improved film quality characteristics include reduced film stress and reduced film shrinkage when compared to conventional FCVD film formation processes.

Abstract translation: 本文所述的实施方案涉及用于形成适用于高纵横比间隙填充应用的可流动化学气相沉积（FCVD）膜的方法。 所描述的各种工艺流程包括用于处理沉积的FCVD膜以改善电介质膜密度和材料组成的离子注入工艺。 离子注入工艺，固化过程和退火工艺可以以各种顺序组合使用，以在器件材料的热预算内的温度下形成具有改善的密度的电介质膜。 与常规的FCVD成膜方法相比，改进的膜质量特性包括膜应力减小和膜收缩减小。

公开(公告)号：US20160005839A1

公开(公告)日：2016-01-07

申请号：US14754042

申请日：2015-06-29

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. YIEH ,  Srinivas D. NEMANI ,  Ludovic GODET ,  Yin FAN ,  Tristan MA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/266 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L29/66803 ,  C23C16/0227 ,  C23C16/04 ,  C23C16/455 ,  C23C16/45525 ,  C23C16/45536 ,  H01J37/32403 ,  H01J37/32422 ,  H01J37/32623 ,  H01L21/02057 ,  H01L21/0228 ,  H01L21/02296 ,  H01L21/02315 ,  H01L21/02334 ,  H01L21/0262 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/266

Abstract: Methods for forming fin structures with desired materials formed on different locations of the fin structure using a selective deposition process for fin field effect transistors (FinFETs) are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes depositing a first material on a substrate having a three-dimensional (3D) structure formed thereon while performing an implantation process to dope a first region of the 3D structure. The first material may be removed and a second material may be deposited on the 3D structure. The second material may selectively grow on a second region of the 3D structure.

Abstract translation: 提供了使用鳍式场效应晶体管（FinFET）的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施例中，在衬底上形成具有期望材料的结构的方法包括在执行植入工艺以掺杂3D结构的第一区域的同时，在其上形成有三维（3D）结构的衬底上沉积第一材料。 可以去除第一材料并且可以将第二材料沉积在3D结构上。 第二材料可以选择性地在3D结构的第二区域上生长。

公开(公告)号：US20150380526A1

公开(公告)日：2015-12-31

申请号：US14469241

申请日：2014-08-26

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Jun XUE ,  Ellie Y. YIEH

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/3205

CPC classification number: H01L29/66795 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using an ion implantation process to define an etching stop layer followed by an etching process for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method for forming a structure on a substrate includes performing an ion implantation process on a substrate having a plurality of structures formed thereon, forming an ion treated region in the structure at an interface between the ion treated region and an untreated region in the structure defining an etch stop layer, and performing a remote plasma etching process to etch the treated region from the substrate to exposed the untreated region.

Abstract translation: 使用离子注入工艺在翅片结构的不同位置形成所需材料的翅片结构的方法，以限定蚀刻停止层，随后进行用于制造用于半导体的鳍状场效应晶体管（FinFET）的三维（3D）堆叠的蚀刻工艺 提供芯片。 在一个实施例中，用于在衬底上形成结构的方法包括在其上形成有多个结构的衬底上执行离子注入工艺，在离子处理区域和未处理区域之间的界面处在该结构中形成离子处理区域 在限定蚀刻停止层的结构中，以及执行远程等离子体蚀刻工艺，以从基板蚀刻经处理的区域以暴露未处理区域。

公开(公告)号：US20150371852A1

公开(公告)日：2015-12-24

申请号：US14730194

申请日：2015-06-03

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Uday MITRA ,  Praburam GOPALRAJA ,  Srinivas D. NEMANI ,  Hua CHUNG

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

Abstract translation: 本公开提供形成具有尺寸在14纳米以下的特征的精确尺寸控制和最小光刻相关误差的纳米结构。 本文提供了自对准多间隔图案（SAMSP）工艺，并且该工艺利用最小光刻曝光工艺，而是采用多次沉积/蚀刻工艺来逐渐减小沿制造工艺在掩模中形成的特征尺寸，直到期望的极小尺寸 在掩模层中形成纳米结构。