公开(公告)号：US20170287752A1

公开(公告)日：2017-10-05

申请号：US15445303

申请日：2017-02-28

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Mehdi VAEZ-IRAVANI ,  Todd EGAN ,  Mangesh BANGAR ,  Concetta RICCOBENE ,  Abdul Aziz KHAJA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Sean S. KANG

IPC: H01L21/67 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/67259 ,  H01L21/265 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/67288 ,  H01L22/20

Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.