Distributed computing system architecture
    71.
    发明授权
    Distributed computing system architecture 有权
    分布式计算系统架构

    公开(公告)号:US07174363B1

    公开(公告)日:2007-02-06

    申请号:US10032222

    申请日:2001-12-19

    Abstract: A computing system architecture is based upon a peer-to-peer, asynchronous model. The architecture specifies a set of infrastructure facilities that comprise an inter-prise operating system. The inter- prise operating system provides all the facilities that make application coding as easy in the peer-to-peer asynchronous model as it is in a hierarchical, synchronous model. Services, which reside in containers, are linked asynchronously by an inter-prise bus and use data from a virtual data store.

    Abstract translation: 计算系统架构基于对等的异步模型。 该体系结构指定了一组基础设施,包括一个跨职业操作系统。 互联操作系统提供使应用编码在对等异步模型中容易的所有设施,就像在分层式同步模型中一样。 驻留在容器中的服务通过奖杯间总线异步链接并使用来自虚拟数据存储的数据。

    Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
    72.
    发明授权
    Access of two synchronous busses with asynchronous clocks to a synchronous single port ram 有权
    通过异步时钟访问两个同步总线到同步单端口RAM

    公开(公告)号:US07170817B2

    公开(公告)日:2007-01-30

    申请号:US10869484

    申请日:2004-06-16

    Applicant: David Levy

    Inventor: David Levy

    CPC classification number: G11C7/1093 G11C7/1006 G11C7/1078

    Abstract: A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.

    Abstract translation: 提供一种用于控制具有异步时钟的两个同步总线对同步单端口随机存取存储器(RAM)的访问的方法和电路。 在一种优选的方法中,总线A的时钟通过控制触发器被切断,然后总线B的时钟被接通,允许控制和数据信号通过简单的多路复用器。 总线B成为RAM的所有者。 之后,通过控制触发器关闭总线B的时钟,然后接通总线A的时钟,使得总线A成为总线的所有者。 这允许总线时钟之间的任何相对速度。

    Privacy and security method and system for a World-Wide-Web site
    73.
    发明申请
    Privacy and security method and system for a World-Wide-Web site 有权
    全球网站的隐私和安全方法和系统

    公开(公告)号:US20060004772A1

    公开(公告)日:2006-01-05

    申请号:US11175402

    申请日:2005-07-07

    Abstract: Personal information of users is used to customize the browsing experiences of the users on a World-Wide-Web site. To ensure privacy of the users' personal information, each user is assigned a unique Universal Anonymous Identifier (UAI). The UAI is generated by a trusted third party and provided to the Web site operator. The Web site operator then indexes the users' personal information by UAI. Only the user has the ability to correlate his/her true identity with his/her personal information.

    Abstract translation: 用户的个人信息用于在万维网站点上定制用户的浏览体验。 为了确保用户个人信息的隐私,每个用户都被分配一个唯一的通用匿名标识符(UAI)。 UAI由可信赖的第三方生成并提供给网站运营商。 网站运营商然后用UAI索引用户的个人信息。 只有用户有能力将他/她的真实身份与他/她的个人信息相关联。

    System and method for providing polarization matching on a cellular communication forward link
    75.
    发明授权
    System and method for providing polarization matching on a cellular communication forward link 失效
    用于在蜂窝通信前向链路上提供极化匹配的系统和方法

    公开(公告)号:US06889061B2

    公开(公告)日:2005-05-03

    申请号:US10181295

    申请日:2001-01-26

    CPC classification number: H04B7/0615 H04B7/0617 H04B7/10

    Abstract: A base station for a wireless communication system is capable of transmitting signals that match the polarization state of a mobile station by including an antenna arrangement having at least one set of transmit antenna elements and at least one set of receive antenna elements, a transformation mechanism having at least one antenna port coupled to the antenna arrangement and at least one beam port, and an adaptive measurement and control mechanism coupled to the transmit and receive antenna port signals and configured to measure and adaptively control attributes of the transmit and receive antenna port signals.

    Abstract translation: 用于无线通信系统的基站能够通过包括具有至少一组发射天线元件和至少一组接收天线元件的天线装置来发送与移动台的偏振状态相匹配的信号,转换机构具有 耦合到所述天线装置和至少一个波束端口的至少一个天线端口,以及耦合到所述发射和接收天线端口信号并被配置为测量和自适应地控制所述发射和接收天线端口信号的属性的自适应测量和控制机构。

    Integrateable optical interleaver and de-interleaver
    76.
    发明申请
    Integrateable optical interleaver and de-interleaver 失效
    可整合光交织器和解交织器

    公开(公告)号:US20050053320A1

    公开(公告)日:2005-03-10

    申请号:US10657862

    申请日:2003-09-09

    Abstract: A proposed integrateable optical interleaver includes an input Y-branch coupler and at least two multi-section optical couplers. The multi-section optical couplers of the interleaver include at least three substantially similar optical couplers, adjacent ones of the optical couplers interconnected via at least one set of waveguides. The interleaver of the present invention comprises a highly compact and fabrication-robust form that is capable of being integrated onto a single planar lightwave circuit.

    Abstract translation: 所提出的可组合光交错器包括输入Y分支耦合器和至少两个多段光耦合器。 交织器的多段光耦合器包括至少三个基本相似的光耦合器,通过至少一组波导互连的相邻光耦合器中的相邻光耦合器。 本发明的交织器包括能够集成到单个平面光波电路上的高度紧凑且制造稳健的形式。

    Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
    78.
    发明申请
    Access of two synchronous busses with asynchronous clocks to a synchronous single port ram 有权
    通过异步时钟访问两个同步总线到同步单端口RAM

    公开(公告)号:US20050021899A1

    公开(公告)日:2005-01-27

    申请号:US10869484

    申请日:2004-06-16

    Applicant: David Levy

    Inventor: David Levy

    CPC classification number: G11C7/1093 G11C7/1006 G11C7/1078

    Abstract: A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.

    Abstract translation: 提供一种用于控制具有异步时钟的两个同步总线对同步单端口随机存取存储器(RAM)的访问的方法和电路。 在一种优选的方法中,总线A的时钟通过控制触发器被切断,然后总线B的时钟被接通,允许控制和数据信号通过简单的多路复用器。 总线B成为RAM的所有者。 之后,通过控制触发器关闭总线B的时钟,然后接通总线A的时钟,使总线A成为总线的所有者。 这允许总线时钟之间的任何相对速度。

    Compact keypad system and method
    79.
    发明授权
    Compact keypad system and method 失效
    紧凑型键盘系统和方法

    公开(公告)号:US5612690A

    公开(公告)日:1997-03-18

    申请号:US71242

    申请日:1993-06-03

    Applicant: David Levy

    Inventor: David Levy

    Abstract: In a key pad key cap symbols are placed at the interstices between key caps as well as at their centers. The key pad electronics are designed to register simultaneously actuated key caps at an interstice as an input uniquely associated with the symbol locate at the interstice. The linear dimension of a row of key caps are approximately one-half that of a conventional key cap requiring approximately two key caps to form a linear dimension sizable enough to comfortably accommodate the tip of an adult finger. Additionally, the symbols located at the centers of key caps are elevated slightly, allowing unimpeded and ergonomic access to individual keys as well as the interstices.

    Abstract translation: 在键盘上,键帽符号被放置在键帽之间的间隙以及它们的中心处。 键盘电子设备被设计为在空隙处将同时激活的键帽注册为与在空隙处的符号定位唯一相关联的输入。 一排键帽的直线尺寸约为传统键帽的一半,其需要大约两个键帽,以形成足够大的直线尺寸,以舒适地容纳成人手指的尖端。 此外,位于键帽中心的符号略微升高,允许无阻碍和符合人体工程学的访问单个键以及间隙。

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