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公开(公告)号:US10589522B2
公开(公告)日:2020-03-17
申请号:US15948565
申请日:2018-04-09
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Scott A. Linn , George H. Corrigan, III , Michael W. Cumbie
Abstract: A fluidic die may include a number of actuators. The number of actuators form a number of primitives. The fluidic die may include a digital-to-analog converter (DAC) to drive a number of the delay circuits. The delay circuits delay a number of activation pulses that activate the actuators associated with the primitives to reduce peak power demands of the fluidic die. A number of delay circuits may be coupled to each primitive.
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公开(公告)号:US20190126632A1
公开(公告)日:2019-05-02
申请号:US16094638
申请日:2016-07-19
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Daryl E. Anderson , James Michael Gardner , Berkeley Fisher , Scott A. Linn
Abstract: In one example, a fluid level sensor includes control logic, and an array of sensing locations to detect a level of fluid in a container. The array of sensing locations include a number of memory cells located at a number of sensing locations in the array of sensing locations, a word line coupled to the memory cells, a bit line coupled to the memory cells, and a pre-charge circuit coupled to the word line and the bit line. The control logic instructs a number FETs coupled to a bit line to disconnect from a number of the memory cells, and power up the memory cells to cause the memory cells to take a first state or a second state. The control logic outputs the state of the memory cells to a Pre-charge processing device. The state of the memory cells defines the level of the fluid in the container.
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公开(公告)号:US20190016127A1
公开(公告)日:2019-01-17
申请号:US15948565
申请日:2018-04-09
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Scott A. Linn , George H. Corrigan III , Michael W. Cumbie
Abstract: A fluidic die may include a number of actuators. The number of actuators form a number of primitives. The fluidic die may include a digital-to-analog converter (DAC) to drive a number of the delay circuits. The delay circuits delay a number of activation pulses that activate the actuators associated with the primitives to reduce peak power demands of the fluidic die. A number of delay circuits may be coupled to each primitive.
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公开(公告)号:US20170355188A1
公开(公告)日:2017-12-14
申请号:US15687694
申请日:2017-08-28
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Daryl E. Anderson , George H. Corrigan , Scott A. Linn
CPC classification number: B41J2/04541 , B41J2/0458 , B41J2/14072 , B41J2/14112 , B41J2/14153 , B41J2/155 , B41J2/17546 , B41J2002/14491 , B41J2202/13 , B41J2202/19 , B41J2202/20
Abstract: A fluidic die includes a number of sensors to measure properties of a number of property control elements associated with the printhead die, a pass gate to communicate a number of signals to an application specific integrated circuit (ASIC) via an analog bus using control logic associated with the pass gate, and a bi-directional configuration bus coupled to the fluidic die to transmit a number of control signals to property control elements located on the fluidic die.
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公开(公告)号:US11969995B2
公开(公告)日:2024-04-30
申请号:US18222354
申请日:2023-07-14
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Scott A. Linn , James Michael Gardner , Michael W. Cumbie
IPC: B41J2/045
CPC classification number: B41J2/04536 , B41J2/04586 , B41J2/04541
Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.
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公开(公告)号:US11938722B2
公开(公告)日:2024-03-26
申请号:US17471844
申请日:2021-09-10
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Scott A. Linn , James Michael Gardner , Michael W. Cumbie
IPC: B41J2/045
CPC classification number: B41J2/04536 , B41J2/04586 , B41J2/04541
Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.
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公开(公告)号:US20230373208A1
公开(公告)日:2023-11-23
申请号:US18228321
申请日:2023-07-31
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: James Michael Gardner , Scott A. Linn , John Rossi , Erik D. Ness
CPC classification number: B41J2/04541 , B41J2/04521 , B41J2/0458 , B41J2/04581 , B41J2/14072 , B41J2/14201 , B41J2002/14491 , G11C13/0069
Abstract: A communicating print component a print head comprising a number of memory bits and a single lane analog bus conductively coupling the number of memory bits to a pad located on the exterior of the print head. The pad is to transmit an electrical signal from the number of memory bits, wherein the electrical signal indicates a combination of all selected bits of the number of memory bits.
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公开(公告)号:US11780223B2
公开(公告)日:2023-10-10
申请号:US17868164
申请日:2022-07-19
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: James Michael Gardner , John Rossi , Scott A. Linn
IPC: B41J2/045
CPC classification number: B41J2/04541 , B41J2/04586
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of contact pads, a plurality of pulldown devices, and control logic. The plurality of contact pads include a first contact pad and a second contact pad. Each of the pulldown devices is electrically coupled to a corresponding contact pad. The control logic enables at least a portion of the pulldown devices in response to both a logic low signal on the first contact pad and a logic low signal on the second contact pad.
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公开(公告)号:US11738562B2
公开(公告)日:2023-08-29
申请号:US17864662
申请日:2022-07-14
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: James Michael Gardner , Scott A. Linn , Stephen D. Panshin , Jefferson P. Ward , David Owen Roethig , David N. Olsen , Anthony D. Studer , Michael W. Cumbie , Sirena Chi Lu
IPC: B41J2/175 , B41J29/393 , G01L23/08 , G06F13/42 , G06F21/44 , G06K15/00 , B33Y50/00 , G03G15/08 , G06K15/10 , G06F9/30 , G06F21/62 , H04L9/08 , H04L9/32
CPC classification number: B41J2/17546 , B33Y50/00 , B41J2/1752 , B41J2/1753 , B41J2/17513 , B41J2/17523 , B41J2/17526 , B41J2/17553 , B41J2/17556 , B41J2/17559 , B41J2/17566 , B41J29/393 , G01L23/08 , G03G15/0856 , G03G15/0863 , G06F9/30105 , G06F13/42 , G06F13/4282 , G06F21/44 , G06F21/62 , G06K15/102 , G06K15/4075 , H04L9/0819 , H04L9/3242 , B41J2002/17516 , B41J2002/17579 , B41J2002/17586 , B41J2202/13 , B41J2202/20 , G05B2219/49023 , G06F2213/0016 , G06F2213/40
Abstract: A logic circuitry package for a replaceable print apparatus component comprises an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. The logic circuit may be configured to identify, from a command stream received from the print apparatus, parameters including a class parameter, and/or identify, from the command stream, a read request, and output, via the interface, a count value in response to a read request, the count value based on identified received parameters.
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公开(公告)号:US11685153B2
公开(公告)日:2023-06-27
申请号:US17991978
申请日:2022-11-22
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Scott A. Linn , James Michael Gardner
CPC classification number: B41J2/04541 , B41J2/0458 , B41J2/04536 , B41J2/04581 , G11C13/003 , G11C13/0038 , G11C13/0069
Abstract: An integrated circuit for a print component including a number of memory bits. The integrated circuit may include a selection circuit to select at least one memory bit of the number of memory bits and fire actuators of a fire pulse group. The integrated circuit may include a memory voltage regulator to provide a write voltage to the at least one memory bit of the number of memory bits.
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