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    PROVIDING VECTOR HORIZONTAL COMPARE FUNCTIONALITY WITHIN A VECTOR REGISTER
    72.
    发明申请
    PROVIDING VECTOR HORIZONTAL COMPARE FUNCTIONALITY WITHIN A VECTOR REGISTER 审中-公开

    公开(公告)号：US20170235572A1

    公开(公告)日：2017-08-17

    申请号：US15585505

    申请日：2017-05-03

    Applicant: INTEL CORPORATION

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Charles R. Yount ,  Suleyman Sair ,  Kshitij A. Doshi

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30018 ,  G06F9/30021 ,  G06F9/30036

    Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.

    MICROSERVICES ARCHITECTURE
    75.
    发明申请
    MICROSERVICES ARCHITECTURE 有权

    公开(公告)号：US20250147822A1

    公开(公告)日：2025-05-08

    申请号：US19010960

    申请日：2025-01-06

    Applicant: Intel Corporation

    Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi

    IPC: G06F9/54 ,  G06F9/50

    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

    BIT MATRIX MULTIPLICATION
    76.
    发明申请
    BIT MATRIX MULTIPLICATION 有权

    公开(公告)号：US20250021621A1

    公开(公告)日：2025-01-16

    申请号：US18754719

    申请日：2024-06-26

    Applicant: Intel Corporation

    Inventor： Dmitry Y. Babokin ,  Kshitij A. Doshi ,  Vadim Sukhomlinov

    IPC: G06F17/16 ,  G06F7/544 ,  G06F9/30

    Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

    Bit matrix multiplication
    77.
    发明授权
    Bit matrix multiplication 有权

    公开(公告)号：US12045308B2

    公开(公告)日：2024-07-23

    申请号：US18083012

    申请日：2022-12-16

    Applicant: Intel Corporation

    Inventor： Dmitry Y. Babokin ,  Kshitij A. Doshi ,  Vadim Sukhomlinov

    IPC: G06F17/16 ,  G06F7/544 ,  G06F9/30

    CPC classification number: G06F17/16 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036

    Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

    Protected data accesses using remote copy operations
    80.
    发明授权
    Protected data accesses using remote copy operations 有权

    公开(公告)号：US11797690B2

    公开(公告)日：2023-10-24

    申请号：US16845885

    申请日：2020-04-10

    Applicant: Intel Corporation

    Inventor： Ned Smith ,  Kshitij A. Doshi ,  Francesc Guim Bernat ,  Kapil Sood ,  Tarun Viswanathan

    IPC: G06F21/60 ,  H04L9/32 ,  G06F15/173

    CPC classification number: G06F21/602 ,  G06F15/17331 ,  H04L9/3268

    Abstract: Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.

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