公开(公告)号：US11061646B2

公开(公告)日：2021-07-13

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Phil Knag ,  Gregory K. Chen ,  Raghavan Kumar ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G06F7/544 ,  G11C8/10 ,  G11C8/08 ,  G11C7/12 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/56 ,  G11C11/4091 ,  G06G7/16 ,  G11C11/419

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US11056593B2

公开(公告)日：2021-07-06

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A Young

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/18 ,  H01L21/3105 ,  H01L21/8252

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US11037614B2

公开(公告)日：2021-06-15

申请号：US16615780

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Ian A. Young ,  Tanay Karnik ,  Daniel H. Morris ,  Kaushik Vaidyanathan

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.

公开(公告)号：US10998495B2

公开(公告)日：2021-05-04

申请号：US16329721

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/10 ,  H01L41/187 ,  H01L41/193 ,  H01L41/20 ,  G11C11/16 ,  H01L41/00 ,  H01L27/22 ,  H01L43/08 ,  H01F10/32 ,  H01L43/02 ,  H01F10/12

Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.

公开(公告)号：US10957844B2

公开(公告)日：2021-03-23

申请号：US16346872

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jasmeet S. Chawla ,  Sasikanth Manipatruni ,  Robert L. Bristol ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00 ,  H03K19/18

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：US20200257965A1

公开(公告)日：2020-08-13

申请号：US16271273

申请日：2019-02-08

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: Techniques are provided for implementing capsule neural networks (NNs) using vector spin neurons. A vector spin neuron according to an embodiment includes a first magnet, polarized in a first direction, to receive a first input current. The first input current is based on an NN input value and weighting factor. The vector spin neuron also includes a second magnet, polarized in a direction orthogonal to the first direction, to receive a second input current. The second input current is based on a second NN input value and weighting factor. The first and second magnets generate spin polarized currents. In some such embodiments, the vector spin neuron further includes a third magnet, which is unpolarized, and a conductor to couple output regions of the first and second magnets to an input region of the third magnet. The third magnet applies a non-linear activation function to the sum of the spin polarized currents.

公开(公告)号：US20200242459A1

公开(公告)日：2020-07-30

申请号：US16262583

申请日：2019-01-30

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Amrita Mathuriya ,  Dmitri Nikonov ,  Ian Young

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06F17/16

Abstract: Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) and a neural processing unit (NPU), coupled to an analog in-memory artificial intelligence (AI) processor. According to an embodiment, the hybrid processor implements an AI instruction set including instructions to perform analog in-memory computations. The AI processor comprises one or more layers, the NN layers including memory circuitry and analog processing circuitry. The memory circuitry is configured to store the weighting factors and the input data. The analog processing circuitry is configured to perform analog calculations on the stored weighting factors and the stored input data in accordance with the execution, by the NPU, of instruction from the AI instruction set. The AI instruction set includes instructions to perform dot products, multiplication, differencing, normalization, pooling, thresholding, transposition, and backpropagation training. The NN layers are configured as convolutional NN layers and/or fully connected NN layers.

公开(公告)号：US10705967B2

公开(公告)日：2020-07-07

申请号：US16160270

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US20200211608A1

公开(公告)日：2020-07-02

申请号：US16349575

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14 ,  H03K19/18 ,  H03K19/185

Abstract: An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

公开(公告)号：US10553268B2

公开(公告)日：2020-02-04

申请号：US16326308

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Ian Young ,  Dmitri Nikonov

IPC: G11C11/16 ,  H01L43/06 ,  H03K19/16 ,  H03K19/18 ,  H01L29/66 ,  H01L29/82

Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.