公开(公告)号：US20220415743A1

公开(公告)日：2022-12-29

申请号：US17358361

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Aleksandar Aleksov ,  Julien Sebot

IPC: H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06 ,  H01L23/00

Abstract: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US11270947B2

公开(公告)日：2022-03-08

申请号：US16698557

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US20220020716A1

公开(公告)日：2022-01-20

申请号：US17488174

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US11133263B2

公开(公告)日：2021-09-28

申请号：US16573948

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H05K1/18

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US20210159163A1

公开(公告)日：2021-05-27

申请号：US16696808

申请日：2019-11-26

Applicant: INTEL CORPORATION

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit (IC) device structure, comprising a host chip having a device layer and one or more first metallization levels over adjacent first and second regions of the device layer. The first metallization levels are interconnected to the device layer. An interconnect chiplet is over the first metallization levels within the first region. The interconnect chiplet comprises a plurality of second metallization levels, and a plurality of third metallization levels over the first metallization levels within the second region and adjacent to the interconnect chiplet. At least one of an interconnect feature dimension or composition differs between one of the second metallization levels and an adjacent one of the third metallization levels.

公开(公告)号：US20210082825A1

公开(公告)日：2021-03-18

申请号：US16573948

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US20210080500A1

公开(公告)日：2021-03-18

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: G01R31/28 ,  G01K7/42

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

公开(公告)号：US20210074620A1

公开(公告)日：2021-03-11

申请号：US16564168

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/54 ,  G03F1/68 ,  G03F1/38

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US10943851B1

公开(公告)日：2021-03-09

申请号：US16706383

申请日：2019-12-06

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Henning Braunisch ,  Johanna Swan

IPC: H01L23/473 ,  G02B6/122 ,  G02B6/13 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48 ,  H05K1/02

Abstract: An integrated circuit device assembly may be formed comprising a reconstituted wafer attached to a base substrate, wherein the base substrate provides thermal management and optical signal routes. In one embodiment, the base substrate may include a plurality of electrical interconnects for electrically coupling integrated circuit devices in the reconstituted wafer. In another embodiment, a plurality of electrical interconnects for electrically coupling integrated circuit devices in the reconstituted wafer may be formed in the reconstituted wafer itself.