公开(公告)号：US20180232311A1

公开(公告)日：2018-08-16

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0831 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F13/1642 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US20180203799A1

公开(公告)日：2018-07-19

申请号：US15408731

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant Nori ,  Sreenivas Subramoney

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F11/34 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/502

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US20180188994A1

公开(公告)日：2018-07-05

申请号：US15393998

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sriseshan Srikanth ,  Lavanya Subramanian ,  Sreenivas Subramoney

IPC: G06F3/06

CPC classification number: G06F12/00

Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.

公开(公告)号：US09195606B2

公开(公告)日：2015-11-24

申请号：US13976248

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Jayesh Guar ,  Nithiyanandan Bashyam ,  Mainak Chaudhuri ,  Sreenivas Subramoney

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/14 ,  G06F12/12

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/128 ,  G06F13/14 ,  G06F2212/62

Abstract: A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.

Abstract translation: 高速缓存存储器驱逐方法包括：将每个高速缓存块的线程感知高速缓存访​​问数据保存在高速缓冲存储器中，其中高速缓存访​​问数据指示高速缓存块被第一线程访问的次数，将高速缓存块与 基于高速缓存块的高速缓存访​​问数据值的多个仓，并且至少部分地基于与高速缓存块候选相关联的区间，从多个高速缓存块候选中选择高速缓存块。

公开(公告)号：US20250117329A1

公开(公告)日：2025-04-10

申请号：US18948214

申请日：2024-11-14

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F12/0893 ,  G06F12/0875

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

公开(公告)号：US12248696B2

公开(公告)日：2025-03-11

申请号：US17340866

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Saurabh Jain ,  Srivatsa Rangachar Srinivasa ,  Akshay Krishna Ramanathan ,  Gurpreet Singh Kalsi ,  Kamlesh R. Pillai ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F7/523

Abstract: Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

公开(公告)号：US12242721B2

公开(公告)日：2025-03-04

申请号：US17214534

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Aravinda Prasad ,  Sandeep Kumar ,  Sreenivas Subramoney ,  Andy Rudoff

IPC: G06F3/06

Abstract: Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level being lower than the first level.

公开(公告)号：US12189559B2

公开(公告)日：2025-01-07

申请号：US16913370

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Anirud Thyagharajan ,  Prashant Laddha ,  Om Omer ,  Sreenivas Subramoney

IPC: G06F13/40 ,  G06V10/82

Abstract: Exemplary embodiments maintain spatial locality of the data being processed by a sparse CNN. The spatial locality is maintained by reordering the data to preserve spatial locality. The reordering may be performed on data elements and on data for groups of co-located data elements referred to herein as “chunks”. Thus, the data may be reordered into chunks, where each chunk contains data for spatially co-located data elements, and in addition, chunks may be organized so that spatially located chunks are together. The use of chunks helps to reduce the need to re-fetch data during processing. Chunk sizes may be chosen based on the memory constraints of the processing logic (e.g., cache sizes).

公开(公告)号：US20240103878A1

公开(公告)日：2024-03-28

申请号：US17953184

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Sufiyan Syed ,  Adithya Ranganathan ,  Sreenivas Subramoney

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3867 ,  G06F9/3806

Abstract: An example of an integrated circuit may include a first execution cluster, a second execution cluster that is one or more of narrower and shallower as compared to the first execution cluster, and circuitry to selectively steer instructions to the first execution cluster and the second execution cluster based on branch misprediction information. Other embodiments are disclosed and claimed.

公开(公告)号：US20240103874A1

公开(公告)日：2024-03-28

申请号：US17951859

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Jayesh Gaur

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/381 ,  G06F9/30065 ,  G06F9/325

Abstract: Methods and apparatus for instruction elimination through hardware driven memoization of loop instances. A hardware-based loop memoization technique learns repeating sequences of loops and transparently removes instructions for the loop instructions from instruction sequences while making their output available to dependent instructions as if the loop instructions had been executed. A path-based predictor is implemented at the front-end to predict these loop instances and remove their instructions from instruction sequences. A novel memoization prediction micro-operation (Uop) is inserted into the instruction sequence for instances of loops that are predicted to be memoized. The memoization prediction Uop is used to compare the input signature (expected set of input values for the loop) with the actual signature to determine correct and incorrect predictions. The input signature learnt is based on all live-ins of a loop, both explicit register-based live-ins as well as loads to memory in the loop body that determine code path and outputs.