公开(公告)号：US11042462B2

公开(公告)日：2021-06-22

申请号：US16559999

申请日：2019-09-04

Applicant: International Business Machines Corporation

Inventor： Anthony Thomas Sofia ,  Peter Sutton ,  Robert W. St. John ,  Matthias Klein

IPC: G06F9/34 ,  G06F9/54 ,  G06F11/34 ,  G06F9/32 ,  G06F11/07

Abstract: Identifying computer program execution characteristics for determine relevance of pattern instruction executions to determine characteristics of a computer program. Filters are utilized to determine which subsequent occurrences of execution of at least one computer instruction are relevant to a counter based on execution characteristics of the at least one computer instruction where the counter counts the subsequent occurrences of execution of at least one computer instruction following prior executions of the same at least one computer instruction.

公开(公告)号：US11005496B2

公开(公告)日：2021-05-11

申请号：US16668061

申请日：2019-10-30

Applicant: International Business Machines Corporation

Inventor： Anthony T. Sofia ,  Matthias Klein ,  Jonathan D. Bradbury ,  Peter Sutton

IPC: H03M7/34 ,  H03M7/30 ,  G06F9/38 ,  G06F15/173

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

公开(公告)号：US10985778B2

公开(公告)日：2021-04-20

申请号：US16741974

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Timothy Siegel ,  Mark Farrell ,  Bruce Giamei ,  Matthias Klein ,  Ashutosh Misra ,  Simon Weishaupt ,  Girish Gopala Kurup

IPC: H03M7/34 ,  H03M13/01 ,  G06F9/50 ,  H03M13/00 ,  H03M7/40 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  H03M7/30

Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

公开(公告)号：US10915461B2

公开(公告)日：2021-02-09

申请号：US16292762

申请日：2019-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Robert J. Sonnelitter, III ,  Matthias Klein ,  Craig Walters ,  Kevin Lopes ,  Michael A. Blake ,  Tim Bronson ,  Kenneth Klapproth ,  Vesselina Papazova ,  Hieu T Huynh

IPC: G06F12/126 ,  G06F12/084 ,  G06F12/0811

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

公开(公告)号：US20200379760A1

公开(公告)日：2020-12-03

申请号：US16423713

申请日：2019-05-28

Applicant: International Business Machines Corporation

Inventor： Christian Jacobi ,  Matthias Klein ,  Martin Recktenwald ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC: G06F9/30 ,  G06F12/0815

Abstract: In one example implementation according to aspects of the present disclosure, a computer-implemented method for executing a load instruction with a timeout includes receiving, by a processing device, the load instruction. The method further includes attempting, by the processing device, to load a lock on a cache line of a memory. The method further includes determining, by the processing device, whether the timeout has expired prior to a successful loading of the lock on the cache line. The method further includes , responsive to determining that the timeout has expired, executing, by the processing device, another instruction instead of loading the lock on the cache line.

公开(公告)号：US20200272565A1

公开(公告)日：2020-08-27

申请号：US16286861

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Ashutosh Misra ,  Girish Gopala Kurup

IPC: G06F12/0831 ,  G06F13/28 ,  G06F9/38

Abstract: A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.

公开(公告)号：US20200272491A1

公开(公告)日：2020-08-27

申请号：US16286990

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Bruce Conrad Giamei ,  Anthony Thomas Sofia ,  Mark S. Farrell ,  Scott Swaney ,  Timothy Slegel

IPC: G06F9/455 ,  G06F8/71 ,  G06F9/48 ,  G06F9/38

Abstract: A system is provided and includes a plurality of machines. The plurality of machines includes a first generation machine and a second generation machine. Each of the plurality of machines includes a machine version. The first generation machine executes a first virtual machine and a virtual architecture level. The second generation machine executes a second virtual machine and the virtual architecture level. The virtual architecture level provides a compatibility level for a complex interruptible instruction to the first and second virtual machines. The compatibility level is architected for a lowest common denominator machine version across the plurality of machines. The compatibility level includes a lowest common denominator indicator identifying the lowest common denominator machine version.

公开(公告)号：US10673460B1

公开(公告)日：2020-06-02

申请号：US16286703

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Girish Gopala Kurup ,  Matthias Klein ,  Anthony Thomas Sofia ,  Jonathan D. Bradbury ,  Ashutosh Misra ,  Christian Jacobi ,  Deepankar Bhattacharjee

IPC: H03M7/00 ,  H03M7/40 ,  G06F9/38 ,  G06F9/54

Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.

公开(公告)号：US20190354409A1

公开(公告)日：2019-11-21

申请号：US16527441

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Brenton F. Belmar ,  Christian Jacobi ,  Matthias Klein ,  Peter G. Sutton

IPC: G06F9/50

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.

公开(公告)号：US10430246B2

公开(公告)日：2019-10-01

申请号：US15873963

申请日：2018-01-18

Applicant: International Business Machines Corporation

Inventor： Brenton F. Belmar ,  Christian Jacobi ,  Matthias Klein ,  Peter G. Sutton

IPC: G06F9/50

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator. An output work package is provided from the hardware accelerator in groups of one or more pages to the application.