公开(公告)号：US20170286360A1

公开(公告)日：2017-10-05

申请号：US15083518

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4295 ,  G06F13/385 ,  G06F13/4022

Abstract: An example system for side band communication can include a processor, a system-on-chip (SOC), and a repeater communicatively coupled to the processor and the SOC. The repeater can receive packets from a first transceiver. The repeater can also detect a pattern in the packets to identify a guest protocol. The repeater can further send the packets from the first transceiver to the SOC via a second transceiver based on the identified guest protocol.

公开(公告)号：US09652351B2

公开(公告)日：2017-05-16

申请号：US14582160

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Karthi R. Vadivelu

IPC: G06F3/00 ,  G06F11/30 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H02J7/00

CPC classification number: G06F11/3051 ,  G06F13/387 ,  G06F13/4077 ,  G06F13/4295 ,  H02J7/0052 ,  H02J2007/0062

Abstract: The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus comprises a USB Type-C port and a USB receiver detector. A charger and a remote host are differentiated based on the USB receiver detector.

公开(公告)号：US20160378154A1

公开(公告)日：2016-12-29

申请号：US14752225

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F1/26 ,  G06F13/42 ,  H02J7/00

CPC classification number: G06F1/266 ,  G06F13/42 ,  H02J7/045 ,  H02J2007/0062 ,  H02J2007/0096

Abstract: Techniques for mitigating voltage offsets are described herein. A method for mitigating voltage offset includes receiving, via a sensor, charging current information. The method also includes adjusting, via a common mode adjustment circuitry, a common mode voltage based on charging current information and a physical layer circuit mode.

Abstract translation: 本文描述了用于减轻电压偏移的技术。 减轻电压偏移的方法包括经由传感器接收充电电流信息。 该方法还包括通过共模调整电路调整基于充电电流信息和物理层电路模式的共模电压。

公开(公告)号：US20160283423A1

公开(公告)日：2016-09-29

申请号：US14668706

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Karthi R. Vadivelu

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F11/3656 ,  G06F13/4068 ,  G06F13/4282

Abstract: A system, method and apparatus for enabling a closed chassis debug control interface are disclosed. In one embodiment, the system comprises a debug mode control (DCI) unit; a Type-C connector; a Universal Serial Bus (USB) physical (phy) interface coupled to the connector; and interface logic coupled to the DCI unit and the USB phy interface to exchange debug control interface (DCI) signaling between the connector and the DCI unit.

Abstract translation: 公开了一种用于启用封闭式机箱调试控制接口的系统，方法和装置。 在一个实施例中，系统包括调试模式控制（DCI）单元; C型连接器; 耦合到连接器的通用串行总线（USB）物理（phy）接口; 以及耦合到DCI单元和USB phy接口的接口逻辑，以在连接器和DCI单元之间交换调试控制接口（DCI）信令。

公开(公告)号：US12199623B2

公开(公告)日：2025-01-14

申请号：US17204792

申请日：2021-03-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Noam Familia

IPC: H03L7/099 ,  G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H03L7/093

Abstract: A digital phase spacing detector with programmable delay lines is described. Each programmable delay line receives a clock. The output of the programmable delay lines is compared by a logic and then passed through a glitch detector. Each of the clocks pass through the programmable delay lines that are tuned to a point where the clock edges at the output of the delay lines are aligned and glitches start appearing at the output of the logic. A calibration scheme uses replica cells (replica of VCO cells) in the measurement path. The calibration scheme calculates the average of clock phase differences through a digital control replica buffer, and this average clock phase difference is applied to the VCO delay stage cells. The PLL is then allowed to relock with the calibrated VCO delay stage cells. This process can be repeated several times to reduce the phase errors between the clock phases.

公开(公告)号：US20220070522A1

公开(公告)日：2022-03-03

申请号：US17523502

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Nausheen Ansari ,  Howard Heck ,  Amit Kumar Srivastava

IPC: H04N21/43 ,  H04N21/422 ,  G06F13/38

Abstract: Embodiments relate to a controller subsystem that includes a virtual reality (VR) subsystem to: identify data received from a peripheral device as related to an audio/visual (A/V) function of the peripheral device; direct, based on the identification that the data is related to the A/V function of the peripheral device, the data to be stored in a memory subsystem of the controller subsystem; and facilitate transmission of an indication of a storage location of the data in the memory subsystem to a host system that is communicatively coupled with the controller subsystem. The controller subsystem further includes a graphics engine to: identify, in a message received from the host system based on the transmission of the indication of the storage location of the data, instructions related to rendering the data; and generate, based on the data received from the peripheral device, rendered data. Other embodiments may be described and claimed.

公开(公告)号：US20220004516A1

公开(公告)日：2022-01-06

申请号：US17479001

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

公开(公告)号：US20210218404A1

公开(公告)日：2021-07-15

申请号：US17196806

申请日：2021-03-09

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: H03L7/087 ,  H03L7/23

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

公开(公告)号：US11030142B2

公开(公告)日：2021-06-08

申请号：US15635299

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

公开(公告)号：US10979055B2

公开(公告)日：2021-04-13

申请号：US16780790

申请日：2020-02-03

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03L1/00 ,  H03K3/03 ,  H03L7/099

Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.