公开(公告)号：US20180060123A1

公开(公告)日：2018-03-01

申请号：US15252511

申请日：2016-08-31

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Israel Hirsh ,  Efraim Rotem ,  Doron Rajwan ,  Avinash N. Ananthakrishnan ,  Natanel Abitan ,  Ido Melamed ,  Guy M. Therien

IPC: G06F9/48

CPC classification number: G06F9/4893 ,  G06F1/32 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5094 ,  Y02D10/24

Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

公开(公告)号：US20170010656A1

公开(公告)日：2017-01-12

申请号：US15270208

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/32 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明涉及具有多个核心的处理器和耦合到核心并且包括多个分区的高速缓冲存储器。 处理器还可以包括基于在至少一个核上执行的工作负载的存储器有界性来动态地改变高速缓存存储器的大小的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US09513688B2

公开(公告)日：2016-12-06

申请号：US13844815

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Jeremy J. Shrall ,  Avinash N. Ananthakrishnan

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3206 ,  Y02D10/126

Abstract: A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.

Abstract translation: 可扩展性算法使处理器初始化性能指标计数器，在第一时间信号的初始频率下操作第一持续时间，并且基于性能指标计数器确定第一处理核心的初始性能。 该算法然后可以使处理器在第一时钟信号的第二频率下工作持续第二持续时间，并且基于性能指标计数器确定第一处理核心的第二性能。 可以基于初始性能和第二性能来确定第一处理核心的性能可扩展性，并且可以基于所确定的可扩展性来改变诸如一个或多个时钟频率和/或供电电压的操作参数。

公开(公告)号：US09471490B2

公开(公告)日：2016-10-18

申请号：US14840639

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/28

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US09354692B2

公开(公告)日：2016-05-31

申请号：US14451807

申请日：2014-08-05

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/26 ,  G06F1/32 ,  G11C7/22

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。

公开(公告)号：US09235254B2

公开(公告)日：2016-01-12

申请号：US13780087

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/16

Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在多域处理器的控制器中确定多域处理器的第二域的温度是否大于节流阀阈值和跨域之和的方法 余量，如果是，则将多域处理器的第一域的频率降低所选择的量。 以这种方式，由于域的热耦合，可以允许第二域的温度降低。 描述和要求保护其他实施例。

公开(公告)号：US20160004291A1

公开(公告)日：2016-01-07

申请号：US14855553

申请日：2015-09-16

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.