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公开(公告)号：US20170285703A1
公开(公告)日：2017-10-05
申请号：US15623536
申请日：2017-06-15
Applicant: Intel Corporation
Inventor： Israel Diamand , Asaf Rubinstein , Arik Gihon , Tal Kuzi , Tomer Ziv , Nadav Shulman
CPC classification number: G06F1/3296 , G06F1/26 , G06F1/3228 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
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公开(公告)号：US20170090945A1
公开(公告)日：2017-03-30
申请号：US14866584
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Doron Rajwan , Eliezer Weissmann , Yoni Aizik , Itai Feit , Tal Kuzi , Tomer Ziv , Nadav Shulman
CPC classification number: G06F11/3024 , G01V11/002 , G06F1/3228 , G06F1/324 , G06F9/5094 , G06F11/3058 , G06F11/3409 , G06F11/3419 , G06F11/3452 , G06F11/348 , G06F2201/88
Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20160252952A1
公开(公告)日：2016-09-01
申请号：US14634777
申请日：2015-02-28
Applicant: Intel Corporation
Inventor： Israel Diamand , Asaf Rubinstein , Arik Gihon , Tal Kuzi , Tomer Ziv , Nadav Shulman
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/26 , G06F1/3228 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括耦合到第一核的第一核和电源管理代理（PMA），以包括存储操作列表的静态表，以及多个列，以指定包括 相应的操作子集。 每个流的执行与第一核的相应状态相关联。 PMA包括控制寄存器（CR），其包括多个存储元件以接收第一值和第二值中的一个。 处理器包括执行逻辑，响应于将第一核放入第一状态的命令，当对应的存储元件存储第一值时，执行第一流的操作，并且当第一流处于 相应的元素存储第二个值。 描述和要求保护其他实施例。
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4.发明公开公开(公告)号：US20230418361A1
公开(公告)日：2023-12-28
申请号：US18244748
申请日：2023-09-11
Applicant: Intel Corporation
Inventor： Chen Ranel , Christopher J. Lake , Hem Doshi , Ido Melamed , Vijay Degalahal , Yevgeni Sabin , Reena Patel , Yoav Ben-Raphael , Nimrod Angel , Efraim Rotem , Shaun Conrad , Tomer Ziv , Nir Rosenzweig , Esfir Natanzon , Yoni Aizik , Arik Gihon , Natanel Abitan
IPC: G06F1/324
CPC classification number: G06F1/324
Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.
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公开(公告)号：US10761594B2
公开(公告)日：2020-09-01
申请号：US15623536
申请日：2017-06-15
Applicant: Intel Corporation
Inventor： Israel Diamand , Asaf Rubinstein , Arik Gihon , Tal Kuzi , Tomer Ziv , Nadav Shulman
IPC: G06F1/32 , G06F1/26 , G06F1/3296 , G06F1/3228 , G06F1/324
Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20160048181A1
公开(公告)日：2016-02-18
申请号：US14461039
申请日：2014-08-15
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Doron Rajwan , Dorit Shapira , Nadav Shulman , Tomer Ziv
CPC classification number: G06F1/206 , G01K1/026 , G01K13/00 , G06F1/3206 , G06F1/3234 , G06F1/324
Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心和多个温度传感器，其中每个核心靠近至少一个温度传感器。 该处理器还包括一个功率控制单元（PCU），其包括用于接收包括来自每个温度传感器的相应温度值的温度数据的温度逻辑。 响应于温度数据的最高温度值超过阈值的指示，温度逻辑是根据基于多个核心中的至少两个的指令执行特性的确定的策略来调整多个域频率。 每个域频率与包括多个核心中的至少一个核心的对应域相关联，并且每个域频率是可独立调整的。 描述和要求保护其他实施例。
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7.发明授权Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor 有权用于优化多点微处理器中的频率和性能的方法，装置和系统公开(公告)号：US08769323B2
公开(公告)日：2014-07-01
申请号：US13788547
申请日：2013-03-07
Applicant: Intel Corporation
Inventor： Jose P. Allarey , Varghese George , Sanjeev Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
CPC classification number: G06F15/82 , G06F1/08 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F9/06 , G06F9/30145 , G06F15/76 , Y02D10/126 , Y02D10/16
Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.
Abstract translation: 随着对多核处理器的进展，每个核心都不能容易地确定另一个模具相对于空闲或活动状态的状态。 讨论了在多芯片微处理器中利用接口在多个核心之间传输核心状态的提议。 因此，这通过允许基于利用每个核心状态来设置性能和频率的最佳设置来促进热管理。
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8.发明申请公开(公告)号：US20220179473A1
公开(公告)日：2022-06-09
申请号：US17440688
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Chen Ranel , Christopher J. Lake , Hem Doshi , Ido Melamed , Vijay Degalahal , Yevgeni Sabin , Reena Patel , Yoav Ben-Raphael , Nimrod Angel , Efraim Rotem , Shaun Conrad , Tomer Ziv , Nir Rosenzweig , Esfir Natanzon , Yoni Aizik , Arik Gihon , Natanel Abitan
IPC: G06F1/324
Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.
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公开(公告)号：US09791904B2
公开(公告)日：2017-10-17
申请号：US14461039
申请日：2014-08-15
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Doron Rajwan , Dorit Shapira , Nadav Shulman , Tomer Ziv
CPC classification number: G06F1/206 , G01K1/026 , G01K13/00 , G06F1/3206 , G06F1/3234 , G06F1/324
Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
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公开(公告)号：US09710054B2
公开(公告)日：2017-07-18
申请号：US14634777
申请日：2015-02-28
Applicant: Intel Corporation
Inventor： Israel Diamand , Asaf Rubinstein , Arik Gihon , Tal Kuzi , Tomer Ziv , Nadav Shulman
CPC classification number: G06F1/3296 , G06F1/26 , G06F1/3228 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
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