公开(公告)号：US20200067526A1

公开(公告)日：2020-02-27

申请号：US16563496

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US20190391939A1

公开(公告)日：2019-12-26

申请号：US16285035

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0808 ,  H04L9/06 ,  G06F13/42 ,  G06F11/10 ,  G06F13/40 ,  G06F1/3287 ,  G06F9/445 ,  G06F9/46 ,  G06F12/0831 ,  G06F12/0806 ,  G06F9/30 ,  G06F8/77 ,  G06F8/71 ,  G06F12/0815 ,  G06F12/0813 ,  H04L12/933

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US20190305888A1

公开(公告)日：2019-10-03

申请号：US16428841

申请日：2019-05-31

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L1/00 ,  H04L1/16

Abstract: Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.

公开(公告)号：US20190258600A1

公开(公告)日：2019-08-22

申请号：US16399898

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/42 ,  G06F11/07 ,  G06F13/20 ,  H04Q11/04

Abstract: A retimer apparatus can include a receiver circuit implemented at least partially in hardware; a configuration register comprising a link management bit set, and one or more bit fields for link management bits indicating link management information; bit stream logic implemented at least partially in hardware to encode an ordered set (OS) with one or more link management bits from the configuration register; and a transmitter circuit implemented at least partially in hardware to transmit OS with the one or more link management bits across a link.

公开(公告)号：US20190095380A1

公开(公告)日：2019-03-28

申请号：US16143182

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/42 ,  G06F13/40

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

公开(公告)号：US20190018813A1

公开(公告)日：2019-01-17

申请号：US15949046

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/42 ,  G06F12/1072

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

公开(公告)号：US20180331864A1

公开(公告)日：2018-11-15

申请号：US15721518

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L27/01

CPC classification number: H04L27/01

Abstract: A port of a computing device is to connect to another device over a link and use equalization logic to perform equalization of the link at a plurality of different data rates. The equalization logic may identify that the other device supports bypassing a sequential equalization mode, determine a maximum data rate supported by the devices on the link, and participate in equalization of the link at the maximum supported data rate before equalizing the link at one or more other data rates lower than the maximum supported data rate in the plurality of data rates.

公开(公告)号：US20180248650A1

公开(公告)日：2018-08-30

申请号：US15640449

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L1/00

Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.

公开(公告)号：US20180067855A1

公开(公告)日：2018-03-08

申请号：US15665541

申请日：2017-08-01

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US20180004558A1

公开(公告)日：2018-01-04

申请号：US15198536

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F9/455 ,  G06F12/1081 ,  G06F13/16

CPC classification number: G06F13/1663 ,  G06F9/45533 ,  G06F12/1081 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2212/656

Abstract: Virtual machine (VM) migration in rack scale systems is disclosed. A source shared memory controller (SMC) of implementations includes a direct memory access (DMA) move engine to establish a first virtual channel (VC) over a link with a destination SMC, the destination SMC coupled to a destination node hosting a VM that is migrated to the destination node from a source node coupled to the source SMC, and transmit, via the first VC to the destination SMC, units of data corresponding to the VM and directory state metadata associated with each unit of data. The source SMC includes a demand request component to establish a second VC over the link, receive, via the second VC from the destination SMC, a demand request for one of the units of data corresponding to the VM, and transmit, via the second VC, the requested unit of data and corresponding directory state metadata.