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    MITIGATING SLOW READ DISTURB IN A MEMORY SUB-SYSTEM
    71.
    发明申请
    MITIGATING SLOW READ DISTURB IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220334756A1

    公开(公告)日：2022-10-20

    申请号：US17235216

    申请日：2021-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Giuseppina Puzzilli ,  Saeed Sharifi Tehrani

    IPC: G06F3/06

    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

    Memory sub-system media management operation threshold
    77.
    发明授权
    Memory sub-system media management operation threshold 有权

    公开(公告)号：US11354052B2

    公开(公告)日：2022-06-07

    申请号：US17002070

    申请日：2020-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Jianmin Huang ,  Ashutosh Malshe

    IPC: G06F3/06

    Abstract: An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device.

    Storing page write attributes
    78.
    发明授权
    Storing page write attributes 有权

    公开(公告)号：US11301146B2

    公开(公告)日：2022-04-12

    申请号：US16889712

    申请日：2020-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Ashutosh Malshe ,  Gianni S. Alsasua

    IPC: G06F3/06

    Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.

    Preemptive idle time read scans
    80.
    发明授权
    Preemptive idle time read scans 有权

    公开(公告)号：US11250918B2

    公开(公告)日：2022-02-15

    申请号：US17035149

    申请日：2020-09-28

    Applicant: Micron Technology, Inc.

    Inventor： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

    IPC: G06F12/00 ,  G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

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