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    Memory sub-system data migration
    71.
    发明授权
    Memory sub-system data migration 有权

    公开(公告)号：US11593032B1

    公开(公告)日：2023-02-28

    申请号：US17395695

    申请日：2021-08-06

    Applicant: Micron Technology, Inc.

    Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

    IPC: G06F3/06

    Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

    Temperature management for a memory device using memory trim sets
    73.
    发明授权
    Temperature management for a memory device using memory trim sets 有权

    公开(公告)号：US11567682B2

    公开(公告)日：2023-01-31

    申请号：US16685300

    申请日：2019-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Ting Luo ,  Ankit Vinod Vashi ,  Xiangang Luo ,  Jianmin Huang

    IPC: G06F3/06

    Abstract: Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.

    L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches
    74.
    发明授权
    L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches 有权

    公开(公告)号：US11487653B2

    公开(公告)日：2022-11-01

    申请号：US16586519

    申请日：2019-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Qing Liang

    IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/1045 ,  G06F13/16

    Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

    LOGICAL-TO-PHYSICAL MAPPING
    75.
    发明申请
    LOGICAL-TO-PHYSICAL MAPPING 有权

    公开(公告)号：US20220342829A1

    公开(公告)日：2022-10-27

    申请号：US17859963

    申请日：2022-07-07

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Jianmin Huang

    IPC: G06F12/1009 ,  G06F11/10

    Abstract: A logical to physical (L2P) mapping component can determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both. The L2P mapping component can further cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both.

    PARITY PROTECTION IN NON-VOLATILE MEMORY
    76.
    发明申请
    PARITY PROTECTION IN NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220326858A1

    公开(公告)日：2022-10-13

    申请号：US17228086

    申请日：2021-04-12

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Zhengang Chen

    IPC: G06F3/06

    Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.

    MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES
    77.
    发明申请
    MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES 有权

    公开(公告)号：US20220318086A1

    公开(公告)日：2022-10-06

    申请号：US17216901

    申请日：2021-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

    IPC: G06F11/07

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

    GROWN BAD BLOCK MANAGEMENT IN A MEMORY SUB-SYSTEM
    80.
    发明申请
    GROWN BAD BLOCK MANAGEMENT IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220277802A1

    公开(公告)日：2022-09-01

    申请号：US17747598

    申请日：2022-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Tao Liu ,  Chun Sum Yeung ,  Xiangang Luo

    IPC: G11C29/00 ,  G11C29/52 ,  G11C29/44

    Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.

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