中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

164 records (took 0.036 seconds)

    Method and apparatus for hardware platform identification with privacy protection
    76.
    发明授权
    Method and apparatus for hardware platform identification with privacy protection 有权
    用于具有隐私保护的硬件平台识别的方法和装置

    公开(公告)号：US06952770B1

    公开(公告)日：2005-10-04

    申请号：US09525702

    申请日：2000-03-14

    Applicant: Millind Mittal ,  James Mi

    Inventor： Millind Mittal ,  James Mi

    IPC: G06F21/00 ,  H04L9/28

    CPC classification number: G06F21/73 ,  G06F21/123

    Abstract: A method and apparatus for enabling hardware platform identification while ensuring privacy protection. The apparatus comprises a computer-readable medium that stores computer-executable instructions. Those instructions, when executed by a microprocessor, cause an expected hash value, which is derived from a key and a first identifier for a computer system; to be compared with a hash value, which is derived from the key and a second identifier for a computer system. A microprocessor for executing those instructions may comprise an identifier that identifies the microprocessor, and embedded instructions for comparing a hash value, derived from the identifier and a key, to an expected hash value.

    Abstract translation: 一种用于在确保隐私保护的同时实现硬件平台识别的方法和装置。 该装置包括存储计算机可执行指令的计算机可读介质。 这些指令在由微处理器执行时产生从计算机系统的密钥和第一标识符导出的预期散列值; 与从密钥导出的散列值和计算机系统的第二标识符进行比较。 用于执行这些指令的微处理器可以包括识别微处理器的标识符和用于将从标识符和密钥导出的哈希值与预期散列值进行比较的嵌入指令。

    Controlling access to multiple isolated memories in an isolated execution environment
    77.
    发明授权
    Controlling access to multiple isolated memories in an isolated execution environment 有权
    在独立的执行环境中控制对多个隔离存储器的访问

    公开(公告)号：US06678825B1

    公开(公告)日：2004-01-13

    申请号：US09618738

    申请日：2000-07-18

    Applicant: Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

    Inventor： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

    IPC: G06F1760

    CPC classification number: G06F12/145 ,  G06F12/0831 ,  G06F12/1009 ,  G06F12/1491 ,  G06F21/74 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/1052

    Abstract: The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated area of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration storage checks the access transaction using at least one of the configuration settings and the access information and generates an access grant signal if the access transaction is valid.

    Abstract translation: 本发明提供一种用于控制对隔离执行环境中的多个隔离存储器区域的存储器访问的方法，装置和系统。 页面管理器用于分别将多个页面分发到存储器的多个不同区域。 记忆分为非隔离区和隔离区。 页面管理器位于隔离区内。 此外，存储器所有权页表描述了存储器的每一页，并且还位于存储器的隔离区域中。 页面管理器将一个隔离的属性分配给页面，如果该页面被分发到一个隔离的内存区域。 另一方面，如果页面被分发到存储器的非隔离区域，则页面管理器将非隔离属性分配给页面。 内存所有权页表记录每个页面的属性。 在一个实施例中，具有正常执行模式和隔离执行模式的处理器生成访问事务。 访问事务使用包含与页面和访问信息相关的配置设置的配置存储进行配置。 耦合到配置存储器的访问检查电路使用配置设置和访问信息中的至少一个来检查访问事务，并且如果访问事务有效则生成访问许可信号。

    COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES INSTRUCTIONS SPECIFYING A BUS LOCK
    80.
    发明授权
    COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES INSTRUCTIONS SPECIFYING A BUS LOCK 有权
    使用TLB提供原子性的计算机系统可以指示使用高速缓存或通过出口指令执行出口指令，并显示指定总线锁定的指令

    公开(公告)号：US06430657B1

    公开(公告)日：2002-08-06

    申请号：US09170137

    申请日：1998-10-12

    Applicant: Millind Mittal ,  Martin J. Whittaker ,  Gary N. Hammond ,  Jerome C. Huck

    Inventor： Millind Mittal ,  Martin J. Whittaker ,  Gary N. Hammond ,  Jerome C. Huck

    IPC: G06F1210

    CPC classification number: G06F12/0837 ,  G06F12/1027

    Abstract: Atomic memory operations are provided by using exportable “fetch and add” instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present invention, a CPU includes a default control register that includes IA-32 lock check enable bit (LC) that when set to “1”, causes an IA-32 atomic memory reference to raise an IA-32 intercept lock fault. An IA-32 intercept lock fault handler branches to appropriate code to atomically emulate the instruction. Furthermore, the present invention defines an exportable fetch and add (FETCHADD) instruction that reads a memory location indexed by a first register, places the contents read from the memory location into a second register, increments the value read from the memory location, and stores the sum back to the memory location. Associated with each virtual memory page is a memory attribute that can assume a state of “cacheable using a write-back policy” (WB), “uncacheable” (UC), or “uncacheable and exportable” (UCE). When a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to WB, the FETCHADD is atomically executed by the CPU by obtaining exclusive use of the cache line containing the memory location. However, when a FETCHADD instruction is executed and the memory location accessed is in a page having an attribute set to UCE, the FETCHADD is atomically executed by exporting the FETCHADD instruction to a centralized location, such as a memory controller.

    Abstract translation: 通过使用可导出的“读取和添加”指令以及通过模拟前缀为前缀的IA-32指令来提供原子存储器操作。 根据本发明，CPU包括默认控制寄存器，其包括当设置为“1”时的IA-32锁定检查使能位（LC），导致IA-32原子存储器引用来提升IA-32拦截锁 故障。 IA-32拦截锁定错误处理器分支到适当的代码以原子地模拟指令。 此外，本发明定义了一种读出由第一寄存器索引的存储器位置的可导出的读取和加法（FETCHADD）指令，将从存储器位置读取的内容放入第二寄存器，增加从存储器位置读取的值，并存储 总和回到内存位置。 与每个虚拟内存页面相关联的是一种内存属性，可以采用“可缓存使用回退策略”（WB），“不可缓存”（UC）或“不可缓存和可导出”（UCE））状态。 当执行FETCHADD指令并且访问的存储器位置在具有设置为WB的属性的页面中时，FETCHADD由CPU通过获得包含存储器位置的高速缓存行的排他使用原子地执行。 然而，当执行FETCHADD指令并且访问的存储器位置在具有设置为UCE的属性的页面中时，通过将FETCHADD指令导出到诸如存储器控制器的集中位置来原子地执行FETCHADD。

Patent Agency Ranking