公开(公告)号：US20190043806A1

公开(公告)日：2019-02-07

申请号：US16157108

申请日：2018-10-11

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/04 ,  H01L25/00

Abstract: A method of manufacturing a chip package structure comprising: disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface; forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface; forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars; forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars; and removing the first carrier.

公开(公告)号：US09972554B2

公开(公告)日：2018-05-15

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

公开(公告)号：US20180076179A1

公开(公告)日：2018-03-15

申请号：US15640595

申请日：2017-07-03

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L25/03 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/214 ,  H01L2924/00

Abstract: A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second terminals, a second redistribution layer and through pillars. Each first chip includes a first active surface and first pads located on the first active surface. The first terminals are disposed on the first pads. The first redistribution layer is electrically connected to the first chip. The first encapsulant encapsulates the first chip and exposes top surfaces of the first terminals. The second chip is disposed over the first encapsulant. The second chip includes a second active surface and second pads located on the second active surface. The second terminals are disposed on the second pads. The second redistribution layer is electrically connected to the second chip. The through pillars electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US20180076158A1

公开(公告)日：2018-03-15

申请号：US15600804

申请日：2017-05-22

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.

公开(公告)号：US20170358557A1

公开(公告)日：2017-12-14

申请号：US15434071

申请日：2017-02-16

Applicant: Powertech Technology Inc.

Inventor： Yu-Wei Chen ,  Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/3114 ,  H01L23/04 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A POP structure includes a first package structure, an interposer, and a second package structure. The first package structure includes a first carrier, a first chip, conductive structures, and a first insulation encapsulation. The first carrier has a first surface and a second surface opposite to the first surface. The first chip and the conductive structures are disposed on the first surface of the first carrier. The first insulation encapsulation is formed on the first surface of the first carrier and encapsulates the conductive structures and the first chip. Top surfaces of the conductive structures are exposed through the first insulation encapsulation and are coplanar. The interposer is disposed on and electrically connected to the first package structure. The second package structure is disposed on and electrically connected to the interposer. A manufacturing method of a POP structure is also provided.

公开(公告)号：US11769763B2

公开(公告)日：2023-09-26

申请号：US17384804

申请日：2021-07-26

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.

公开(公告)号：US20230282587A1

公开(公告)日：2023-09-07

申请号：US17994409

申请日：2022-11-28

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2924/1811 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.

公开(公告)号：US11637071B2

公开(公告)日：2023-04-25

申请号：US17159152

申请日：2021-01-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00

Abstract: A package structure, including a conductive element, multiple dies, a dielectric body, a circuit layer and a patterned insulating layer, is provided. The multiple dies are disposed on the conductive element. A portion of the conductive element surrounds the multiple dies. The dielectric body covers the multiple dies. The circuit layer is disposed on the dielectric body. The circuit layer is electrically connected to the multiple dies. The patterned insulating layer covers the circuit layer. A portion of the patterned insulating layer is disposed between the dies that are adjacent. A manufacturing method of a package structure is also provided.

公开(公告)号：US11309283B2

公开(公告)日：2022-04-19

申请号：US17099801

申请日：2020-11-17

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/538 ,  H01L23/36 ,  H01L23/48

Abstract: A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided.

公开(公告)号：US11251170B2

公开(公告)日：2022-02-15

申请号：US16398246

申请日：2019-04-29

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/053 ,  H01L49/02 ,  H01L23/367 ,  H01L23/552

Abstract: A package structure including a frame structure, a die, an encapsulant, a redistribution structure, and a passive component is provided. The frame structure has a cavity. The die is disposed in the cavity. The encapsulant fills the cavity to encapsulate the die. The redistribution structure is disposed on the encapsulant, the die, and the frame structure. The redistribution structure is electrically coupled to the die. The passive component is disposed on the frame structure and electrically coupled to the redistribution structure through the frame structure. A manufacturing method of a package structure is also provided. The frame structure may provide support, reduce warpage, dissipate heat from the die, act as a shield against electromagnetic interference, and/or provide electrical connection for grounding.