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公开(公告)号：US20170147239A1
公开(公告)日：2017-05-25
申请号：US15144435
申请日：2016-05-02
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0652 , G06F3/0653 , G06F3/0679 , G06F12/00 , G06F12/0261
Abstract: This technology relates to a memory system for processing data into a memory device and an operating method of the same. The memory system may include a memory device comprising one or more closed memory blocks each including plural pages, and a controller suitable for generating valid page counts (VPCs) for each closed memory block at least two different time points, generating a VPC offset for each closed memory block between the at least two different time points, selecting a source memory block among the closed memory blocks according to the generated VPC offsets, and performing a garbage collection operation to the selected source memory block.
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72.发明公开公开(公告)号：US20230244616A1
公开(公告)日：2023-08-03
申请号：US18298386
申请日：2023-04-11
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
CPC classification number: G06F13/1668 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F13/4282 , G06F2213/0016
Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.
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公开(公告)号：US20200090778A1
公开(公告)日：2020-03-19
申请号：US16368087
申请日：2019-03-28
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
Abstract: A memory system includes: a memory device including a plurality of memory blocks; a memory; a data classifier suitable for classifying check-pointing information stored in the memory as selective information and mandatory information; and a check-pointing component suitable for performing a control to periodically perform a check-pointing operation of programming the selective information and the mandatory information in a memory block, wherein the check-pointing component performs the check-pointing operation by performing a control to program the mandatory information after programming the selective information.
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74.发明申请公开(公告)号：US20200050368A1
公开(公告)日：2020-02-13
申请号：US16375671
申请日：2019-04-04
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
IPC: G06F3/06 , G06F12/1009
Abstract: A memory system includes a non-volatile memory device including at least one memory blocks storing a data and a controller coupled to the non-volatile memory device. The controller can perform at least one program operation or at least one erase operation within the at least one memory block. The controller can recognize an operation status of the at least one memory block in response to a time consumed for completing the at least one operation, and determine whether the at least one memory block is used and which priority is given to the at least one memory block based at least on the operation status so that the at least one memory block is allocated for a following operation.
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公开(公告)号：US20200042470A1
公开(公告)日：2020-02-06
申请号：US16367974
申请日：2019-03-28
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.
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Patent Agency Ranking
公开(公告)号：US20200042243A1
公开(公告)日：2020-02-06
申请号：US16289833
申请日：2019-03-01
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
IPC: G06F3/06
Abstract: A memory system includes a memory device including plural memory blocks, each including plural pages storing data, and a controller suitable for loading data from first memory blocks among the plural memory blocks to perform command operations corresponding to plural commands and securing second memory blocks among the plural memory blocks to store data updated by the command operations. The controller can exclude the first memory blocks from the second memory blocks.
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公开(公告)号：US20200019497A1
公开(公告)日：2020-01-16
申请号：US16237205
申请日：2018-12-31
Applicant: SK hynix Inc.
Inventor： Hyeong-Ju NA , Jong-Min LEE
IPC: G06F12/02 , G06F3/06 , G06F12/0882
Abstract: A memory system includes: a memory device; a candidate logical block address (LBA) sensor suitable for detecting a start LBA of a sequential workload as a candidate LBA, and, when a ratio of the number of update blocks to a total sum of valid page decrease amounts is less than a first threshold value, caching the candidate LBA in a loop cache; and a garbage collector suitable for performing a garbage collection operation on a victim block, when the number of free blocks in the memory device is less than a second threshold value and greater than or equal to a third threshold value and a start LBA of a subsequent sequential workload is not the same as the cached candidate LBA.
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公开(公告)号：US20190266085A1
公开(公告)日：2019-08-29
申请号：US16179362
申请日：2018-11-02
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE , Beom-Rae JEONG
IPC: G06F12/0804
Abstract: A memory system may include: a nonvolatile memory comprising a plurality of memory blocks, each including a plurality of pages; a volatile memory suitable for temporarily storing data transferred between a host and the nonvolatile memory; and a controller suitable for determining whether to start or end an automatic exclusive mode in response to a request from the host or a result obtained by checking a state of the nonvolatile memory, repeatedly entering into, or exiting from, the automatic exclusive mode in each set cycle when the automatic exclusive mode is started, and exclusively using the volatile memory to perform a merge operation on the nonvolatile memory during an entry period of the automatic exclusive mode in each set cycle.
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公开(公告)号：US20190198119A1
公开(公告)日：2019-06-27
申请号：US16037588
申请日：2018-07-17
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
Abstract: A memory system includes: a memory device including a plurality of memory blocks; a bad memory block detection unit suitable for performing a test read operation on the plurality of memory blocks to detect a bad memory block; and a controller suitable for controlling the memory device to perform a read reclaim operation to the bad memory block according to a result of detecting the bad memory block by the bad memory block detection unit.
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公开(公告)号：US20190188082A1
公开(公告)日：2019-06-20
申请号：US16043683
申请日：2018-07-24
Applicant: SK hynix Inc.
Inventor： Jong-Min LEE
CPC classification number: G06F11/1417 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F11/1407 , G06F11/1441 , G06F12/0246
Abstract: A memory system may include: a nonvolatile memory device including a plurality of memory blocks, each of which includes a plurality of pages, and among which a subset of memory blocks are managed as a system area and remaining memory blocks are managed as a normal area; and a controller may store system data, used to control the nonvolatile memory device, in the system area, and storing boot data, used in a host and normal data updated in a control operation for the nonvolatile memory device, in the normal area, the controller may perform a checkpoint operation each time storage of N number of boot data among the boot data is completed, and may perform the checkpoint operation each time the control operation for the nonvolatile memory device is completed, ‘N’ being a natural number.
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