公开(公告)号：US20190258577A1

公开(公告)日：2019-08-22

申请号：US16123467

申请日：2018-09-06

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE ,  Beom-Rae JEONG

IPC: G06F12/0868 ,  G06F12/0831 ,  G06F3/06

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks each of which includes a plurality of pages; a volatile memory device configured to temporarily store data to be transmitted between a host and the nonvolatile memory device; and a controller configured to enter an exclusive mode in response to a request of the host, a result of checking a state of the nonvolatile memory device, or performing a merge operation on the nonvolatile memory device, exclusively use the volatile memory device to perform the merge operation during an entry period of the exclusive mode, and exit the exclusive mode in response to completing the performing of the merge operation.

公开(公告)号：US20180293006A1

公开(公告)日：2018-10-11

申请号：US15817456

申请日：2017-11-20

Applicant: SK hynix Inc.

Inventor： Beom-Rae JEONG

IPC: G06F3/06

Abstract: A controller includes a memory including one or more command queues for queuing commands according to their type, each command queue operating on a first-in-first-out (FIFO) scheme a first processor suitable for queueing a plurality of commands into a corresponding one among the command queues, and for storing in the memory first and second information about the queued commands; and a second processor suitable for processing the queued command of the respective command queues according to the first and second information of the queued commands.

公开(公告)号：US20180267897A1

公开(公告)日：2018-09-20

申请号：US15726489

申请日：2017-10-06

Applicant: SK hynix Inc.

Inventor： Beom-Rae JEONG

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/608

Abstract: A memory system includes: a memory device; and a controller including a cache which is coupled between a host and the memory device and includes a plurality of storing regions, for determining whether or not a storing region corresponding to address information which is requested by the host exists in the cache among the plurality of the storing regions based on bitmap information which hierarchically represents the plurality of the storing regions.

公开(公告)号：US20190266085A1

公开(公告)日：2019-08-29

申请号：US16179362

申请日：2018-11-02

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE ,  Beom-Rae JEONG

IPC: G06F12/0804

Abstract: A memory system may include: a nonvolatile memory comprising a plurality of memory blocks, each including a plurality of pages; a volatile memory suitable for temporarily storing data transferred between a host and the nonvolatile memory; and a controller suitable for determining whether to start or end an automatic exclusive mode in response to a request from the host or a result obtained by checking a state of the nonvolatile memory, repeatedly entering into, or exiting from, the automatic exclusive mode in each set cycle when the automatic exclusive mode is started, and exclusively using the volatile memory to perform a merge operation on the nonvolatile memory during an entry period of the automatic exclusive mode in each set cycle.

公开(公告)号：US20180307547A1

公开(公告)日：2018-10-25

申请号：US15887263

申请日：2018-02-02

Applicant: SK hynix Inc.

Inventor： Beom-Rae JEONG

IPC: G06F9/54 ,  G06F9/46

CPC classification number: G06F9/546 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/465

Abstract: A controller may include a first processor suitable for sequentially storing commands provided from a host into one of first and second mailboxes of a memory according to types of the commands; and a second processor suitable for serving the commands stored in the first and second mailboxes, wherein, when provided from the host is a first command corresponding to the same logical address as a second command stored in the second mailbox, the first and second commands being of different types, the first processor stores the first command into the first mailbox and stores into the memory a priority information representing the second command having a higher processing priority to the first command, and wherein the second processor serves the commands stored in the first mailbox and the second mailbox by referring to the priority information.