公开(公告)号：US11289346B2

公开(公告)日：2022-03-29

申请号：US16919433

申请日：2020-07-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chen-Yu Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kong-Toon Ng ,  Rui-Feng Tai ,  Bo-Hao Ma

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/3105

Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.

公开(公告)号：US11164755B1

公开(公告)日：2021-11-02

申请号：US16895461

申请日：2020-06-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yung-Ta Li ,  Yi-Chian Liao ,  Kong-Toon Ng ,  Chang-Fu Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.

公开(公告)号：US20200335447A1

公开(公告)日：2020-10-22

申请号：US16919433

申请日：2020-07-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chen-Yu Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kong-Toon Ng ,  Rui-Feng Tai ,  Bo-Hao Ma

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/48

Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.

公开(公告)号：US10679932B2

公开(公告)日：2020-06-09

申请号：US15499446

申请日：2017-04-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367

Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.

公开(公告)号：US20200043908A1

公开(公告)日：2020-02-06

申请号：US16164416

申请日：2018-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chee-Key Chung ,  Chang-Fu Lin ,  Han-Hung Chen ,  Jen-Chieh Hsiao ,  Rung-Jeng Lin ,  Kuo-Hua Yu ,  Hong-Da Chang

IPC: H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00

Abstract: A package stacked structure and a method for fabricating the same are provided. The method includes providing a wiring structure disposed with a carrier and a carrier structure provided with an electronic component. The wiring structure is bonded to the carrier structure via a plurality of conductive elements. An encapsulating layer is formed between the wiring structure and the carrier structure and encapsulates the conductive elements and the electronic component. The carrier is then removed. With the arrangement of the carrier, the structural strength of the wiring structure is improved, and warpage of the wiring structure is prevented before stacking the wiring structure onto the carrier structure.

公开(公告)号：US10522500B2

公开(公告)日：2019-12-31

申请号：US15980255

申请日：2018-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Min Lo ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kuo-Hua Yu ,  Hsiang-Hua Huang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

公开(公告)号：US20180061810A1

公开(公告)日：2018-03-01

申请号：US15372638

申请日：2016-12-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Kuo-Hua Yu ,  Fu-Tang Huang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13541 ,  H01L2224/16013 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17132 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US09607963B2

公开(公告)日：2017-03-28

申请号：US14258361

申请日：2014-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Fu-Tang Huang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17106 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.

公开(公告)号：US20150069605A1

公开(公告)日：2015-03-12

申请号：US14272764

申请日：2014-05-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Hung-Ming Chang ,  Ming-Chin Chuang ,  Fu-Tang Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76895 ,  H01L21/563 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/014

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Abstract translation: 公开了一种半导体器件，其包括：具有多个连接焊盘的衬底; 半导体部件，其具有形成在其表面上并对应于所述连接焊盘的多个焊盘和形成在所述焊盘上的UBM层; 多个导电元件，其各自具有依次形成在所述UBM层上的第一导电部分和第二导电部分，其中所述第二导电部分的宽度小于所述第一导电部分; 以及形成在第二导电部分和连接焊盘之间的多个焊球，用于连接半导体部件和衬底，从而防止在相邻的导电元件之间发生焊料桥接并减小导电元件与UBM层之间的应力。

公开(公告)号：US12278189B2

公开(公告)日：2025-04-15

申请号：US18376652

申请日：2023-10-04

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chih-Ming Huang ,  Kuo-Hua Yu ,  Chang-Fu Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498

Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.