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公开(公告)号：US20150237717A1
公开(公告)日：2015-08-20
申请号：US14453977
申请日：2014-08-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-fu Lin Chang , Chin-Tsai Yao , Ming-Chin Chuang , Ko-Cheng Liu , Fu-Tang Huang
CPC classification number: H05K3/4644 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/181 , H05K1/02 , H05K1/0296 , H05K1/0298 , H05K1/181 , H05K3/284 , H05K2201/0191 , H05K2201/09736 , H05K2201/20 , H05K2203/0353 , H05K2203/0369 , H01L2924/00012 , H01L2924/00
Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.
Abstract translation: 提供一种封装基板，其包括多个电介质层和与电介质层交替堆叠的多个电路层。 至少两个电路层的厚度不同，以防止基板翘曲。
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2.发明申请公开(公告)号：US20170148679A1
公开(公告)日：2017-05-25
申请号：US15424116
申请日：2017-02-03
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Keng-Hung Liu , Fu-Tang Huang
IPC: H01L21/78 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/544
CPC classification number: H01L21/78 , H01L21/561 , H01L23/3178 , H01L23/544 , H01L24/06 , H01L24/17 , H01L2223/54453 , H01L2224/0401 , H01L2224/13022 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/15311 , H01L2224/03 , H01L2224/11 , H01L2924/00
Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.
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公开(公告)号：US09607963B2
公开(公告)日：2017-03-28
申请号：US14258361
申请日：2014-04-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Fu-Tang Huang
IPC: H01L23/00 , H01L21/48 , H01L23/498
CPC classification number: H01L24/81 , H01L21/4846 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05572 , H01L2224/131 , H01L2224/13147 , H01L2224/1601 , H01L2224/16057 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17106 , H01L2224/73204 , H01L2224/81385 , H01L2224/81815 , H01L2924/01029 , H01L2924/35121 , H01L2924/00014 , H01L2924/014 , H01L2924/00012
Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.
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4.发明申请SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF AND SEMICONDUCTOR STRUCTURE 有权半导体器件及其制造方法及其半导体结构公开(公告)号：US20150069605A1
公开(公告)日：2015-03-12
申请号：US14272764
申请日：2014-05-08
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Hung-Ming Chang , Ming-Chin Chuang , Fu-Tang Huang
IPC: H01L23/00 , H01L21/768 , H01L23/498
CPC classification number: H01L21/76895 , H01L21/563 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05558 , H01L2224/05572 , H01L2224/1134 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13005 , H01L2224/13017 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/16057 , H01L2224/16058 , H01L2224/16238 , H01L2224/73204 , H01L2224/81191 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/014
Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.
Abstract translation: 公开了一种半导体器件，其包括：具有多个连接焊盘的衬底; 半导体部件，其具有形成在其表面上并对应于所述连接焊盘的多个焊盘和形成在所述焊盘上的UBM层; 多个导电元件，其各自具有依次形成在所述UBM层上的第一导电部分和第二导电部分，其中所述第二导电部分的宽度小于所述第一导电部分; 以及形成在第二导电部分和连接焊盘之间的多个焊球，用于连接半导体部件和衬底，从而防止在相邻的导电元件之间发生焊料桥接并减小导电元件与UBM层之间的应力。
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公开(公告)号：US09842771B2
公开(公告)日：2017-12-12
申请号：US14272764
申请日：2014-05-08
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Hung-Ming Chang , Ming-Chin Chuang , Fu-Tang Huang
IPC: H01L23/48 , H01L21/768 , H01L23/00 , H01L23/31 , H01L21/56
CPC classification number: H01L21/76895 , H01L21/563 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05558 , H01L2224/05572 , H01L2224/1134 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13005 , H01L2224/13017 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/16057 , H01L2224/16058 , H01L2224/16238 , H01L2224/73204 , H01L2224/81191 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/014
Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.
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Patent Agency Ranking
公开(公告)号：US20150332998A1
公开(公告)日：2015-11-19
申请号：US14564145
申请日：2014-12-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Ko-Cheng Liu , Fu-Tang Huang
IPC: H01L23/498 , H05K1/02
CPC classification number: H01L23/49822 , H01L23/3121 , H01L23/49838 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15174 , H01L2924/181 , H05K1/0298 , H05K2201/0191 , H05K2201/0195 , H01L2924/00012 , H01L2924/00
Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.
Abstract translation: 提供了一种封装基板和封装结构。 包装衬底包括多个电介质层，其中两个具有不同的厚度; 以及与电介质层交替层叠的多个电路层。 因此，避免了现有技术中遇到的包装翘曲。
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7.发明申请SEMICONDUCTOR PACKAGE, SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开半导体封装，半导体基板，半导体结构及其制造方法公开(公告)号：US20150004752A1
公开(公告)日：2015-01-01
申请号：US14085959
申请日：2013-11-21
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Keng-Hung Liu , Fu-Tang Huang
IPC: H01L21/78 , H01L23/544
CPC classification number: H01L21/78 , H01L21/561 , H01L23/3178 , H01L23/544 , H01L24/06 , H01L24/17 , H01L2223/54453 , H01L2224/0401 , H01L2224/13022 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/15311 , H01L2224/03 , H01L2224/11 , H01L2924/00
Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.
Abstract translation: 公开了一种半导体封装，其包括：封装基板; 以倒装芯片的方式设置在封装衬底上的半导体元件; 形成在所述半导体元件的边缘处的止动部; 绝缘层，形成在所述半导体元件的有源表面和所述止动部分上; 以及形成在包装基板和绝缘层之间的密封剂。 绝缘层具有形成在止动部分上并面向封装基板的凹陷部分，使得在可靠性测试期间，凹陷部分可以防止绝缘层和止动部分之间的分层延伸到半导体元件的有源表面。
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公开(公告)号：US09900996B2
公开(公告)日：2018-02-20
申请号：US14453977
申请日：2014-08-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Ko-Cheng Liu , Fu-Tang Huang
CPC classification number: H05K3/4644 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/181 , H05K1/02 , H05K1/0296 , H05K1/0298 , H05K1/181 , H05K3/284 , H05K2201/0191 , H05K2201/09736 , H05K2201/20 , H05K2203/0353 , H05K2203/0369 , H01L2924/00012 , H01L2924/00
Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.
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公开(公告)号：US09520351B2
公开(公告)日：2016-12-13
申请号：US14564145
申请日：2014-12-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Ko-Cheng Liu , Fu-Tang Huang
IPC: H01L23/00 , H01L23/498 , H05K1/02 , H01L23/31
CPC classification number: H01L23/49822 , H01L23/3121 , H01L23/49838 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15174 , H01L2924/181 , H05K1/0298 , H05K2201/0191 , H05K2201/0195 , H01L2924/00012 , H01L2924/00
Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.
Abstract translation: 提供了一种封装基板和封装结构。 包装衬底包括多个电介质层，其中两个具有不同的厚度; 以及与电介质层交替层叠的多个电路层。 因此，避免了现有技术中遇到的包装翘曲。
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10.发明申请FLIP-CHIP PACKAGING SUBSTRATE, FLIP-CHIP PACKAGE AND FABRICATION METHODS THEREOF 审中-公开卷芯片包装基板，卷芯片包装及其制造方法公开(公告)号：US20150235914A1
公开(公告)日：2015-08-20
申请号：US14328092
申请日：2014-07-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Ming-Chin Chuang , Po-Hua Chen , Fu-Tang Huang
CPC classification number: H05K3/4661 , C25D5/02 , C25D5/48 , C25D7/00 , H01L21/4853 , H01L23/49894 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16237 , H01L2224/81191 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2924/3841 , H05K1/111 , H05K3/244 , H05K3/3436 , H05K2201/09745 , H05K2201/099 , H05K2201/10674 , H01L2924/00014 , H01L2924/014
Abstract: A flip-chip packaging substrate is provided, which includes: a substrate body; a plurality of conductive pads formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having a plurality of openings correspondingly exposing a portion of each of the conductive pads; and a metal layer formed on each of the conductive pads in the openings, wherein the metal layer has a top surface having a lowest point lower than a top surface of the insulating layer, and a thickness ratio of the metal layer to the insulating layer is greater than or equal to 1/4 and less than 1, thereby preventing a solder bridge or short circuit from occurring.
Abstract translation: 提供一种倒装芯片封装基板，其包括：基板主体; 形成在所述基板主体的表面上的多个导电焊盘; 绝缘层，其形成在所述基板主体的表面上并且具有多个开口，对应地暴露所述导电焊盘的每一个的一部分; 以及形成在所述开口中的每个所述导电焊盘上的金属层，其中，所述金属层具有比所述绝缘层的顶表面低的最低点的顶表面，并且所述金属层与所述绝缘层的厚度比为 大于或等于1/4且小于1，从而防止发生焊料桥或短路。
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