公开(公告)号：US10096685B2

公开(公告)日：2018-10-09

申请号：US15406913

申请日：2017-01-16

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/167 ,  H01L21/324 ,  H01L21/265 ,  H01L21/762 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US20180233561A1

公开(公告)日：2018-08-16

申请号：US15434610

申请日：2017-02-16

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/10 ,  H01L29/78

Abstract: A system and method for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with Shallow Trench Isolation (STI) in the backgate region of FET with trench contacts is provided. The backgate diffusion region of the FET is split in the middle of the source-backgate side of the LDMOS with a strip of STI. A contact can be drawn across STI strip. The contact etch can be etched through the STI fill. The contact barrier material and trench fill processes can create a metal-semiconductor contact in the outline of the STI.

公开(公告)号：US20170358568A1

公开(公告)日：2017-12-14

申请号：US15665575

申请日：2017-08-01

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Md Iqbal Mahmud

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/747 ,  H01L29/45 ,  H01L29/74 ,  H01L29/06

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/66386 ,  H01L29/7436 ,  H01L29/747

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

公开(公告)号：US20170062518A1

公开(公告)日：2017-03-02

申请号：US15350694

申请日：2016-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L27/16 ,  H01L35/32 ,  H01L21/8238 ,  H01L21/265 ,  H01L35/04 ,  H01L35/34

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 在所述实施例中，通过在CMOS晶体管之间以及嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽来形成嵌入式热电元件。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US20160372516A1

公开(公告)日：2016-12-22

申请号：US15255243

申请日：2016-09-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey R. Debord ,  Henry Litzmann Edwards ,  Kenneth J. Maggio

IPC: H01L27/16 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/768 ,  H01L35/30 ,  H01L35/04

CPC classification number: H01L27/16 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0617 ,  H01L27/092 ,  H01L35/04 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

Abstract translation: 在所述实施例中，可以通过形成有源区域来形成包含CMOS晶体管和嵌入式热电装置的集成电路，该有源区域为CMOS晶体管的NMOS晶体管和PMOS晶体管提供晶体管有源区，并提供n型热电元件和p型 嵌入式热电元件的热电元件。 在n型热电元件和p型热电元件上形成横截面比大于4:1的拉伸接触，以通过金属互连提供到嵌入式热电器件的热节点的电连接和热连接。 拉伸接触通过在电介质层中形成接触沟槽，用接触金属填充接触沟槽并随后从电介质层上方去除接触金属而形成。 拉伸触点与NMOS和PMOS晶体管的触点同时形成。

公开(公告)号：US09461032B1

公开(公告)日：2016-10-04

申请号：US14933661

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/06

CPC classification number: H01L27/0259 ,  H01L29/0626 ,  H01L29/0649 ,  H01L29/7304 ,  H01L29/866

Abstract: A bipolar ESD protection device includes a substrate having a p-type epi layer thereon including an epi region over an n-buried layer (NBL). An n-type isolation tank (iso tank) includes a deep n+ region and NBL for containing an isolated epi region of the epi region. An NPN transistor and an avalanche diode are formed in the isolated epi region. The NPN transistor includes an emitter within a base having a base contact and the collector is a top portion of NBL. The avalanche diode includes a p-type anode region including an anode contact and an n-type cathode region having a cathode contact. The anode region and base are resistively coupled through the epi region. A ground connection couples the emitter to the anode contact and a strike node connection couples the cathode contact to an n+ isolation contact.

Abstract translation: 双极性ESD保护器件包括其上具有p型外延层的衬底，其上包括n掩埋层（NBL）上的外延区域。 n型隔离罐（iso罐）包括深n +区域和NBL，用于容纳epi区域的孤立的epi区域。 在隔离的epi区域中形成NPN晶体管和雪崩二极管。 NPN晶体管包括在具有基极接触的基底内的发射极，并且集电极是NBL的顶部。 雪崩二极管包括包括阳极接触的p型阳极区域和具有阴极接触的n型阴极区域。 阳极区域和基极通过epi区域电阻耦合。 接地连接将发射极耦合到阳极触点，并且击穿节点连接将阴极触点耦合到n +隔离触点。

公开(公告)号：US09437799B2

公开(公告)日：2016-09-06

申请号：US14957314

申请日：2015-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Kenneth James Maggio ,  Toan Tran ,  Jihong Chen ,  Jeffrey R. Debord

IPC: H01L27/00 ,  H01L35/34 ,  H01L27/16 ,  H01L27/092 ,  H01L27/108

CPC classification number: H01L35/34 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/10876 ,  H01L27/16 ,  H01L29/34 ,  H01L35/04 ,  H01L37/00 ,  H01L2924/13091

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract translation: 可以通过在隔离沟槽中形成场氧化物来隔离嵌入式热电装置的CMOS晶体管和热电元件来形成包含CMOS晶体管和嵌入式热电装置的集成电路。 将N型掺杂剂注入到衬底中以在n型热电元件中提供至少1×1018cm-3n型掺杂剂和在n型热电元件之间的场氧化物下的衬底。 P型掺杂剂被注入到衬底中以在p型热电元件中提供至少1×1018cm-3p型掺杂剂，并且在p型热电元件之间的场氧化物之下提供衬底。 在形成场氧化物的隔离沟槽之后，在隔离沟槽中形成介电材料之前和/或在形成场氧化物之后，可以在形成场氧化物之前，注入n型掺杂剂和p型掺杂剂 。

公开(公告)号：US20160155925A1

公开(公告)日：2016-06-02

申请号：US14957314

申请日：2015-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Kenneth James Maggio ,  Toan Tran ,  Jihong Chen ,  Jeffrey R. Debord

IPC: H01L35/34 ,  H01L27/16

CPC classification number: H01L35/34 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/10876 ,  H01L27/16 ,  H01L29/34 ,  H01L35/04 ,  H01L37/00 ,  H01L2924/13091

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract translation: 可以通过在隔离沟槽中形成场氧化物来隔离嵌入式热电装置的CMOS晶体管和热电元件来形成包含CMOS晶体管和嵌入式热电装置的集成电路。 将N型掺杂剂注入到衬底中以在n型热电元件中提供至少1×1018cm-3n型掺杂剂和在n型热电元件之间的场氧化物下的衬底。 P型掺杂剂被注入到衬底中以在p型热电元件中提供至少1×1018cm-3p型掺杂剂，并且在p型热电元件之间的场氧化物之下提供衬底。 在形成场氧化物的隔离沟槽之后，在隔离沟槽中形成介电材料之前和/或在形成场氧化物之后，可以在形成场氧化物之前，注入n型掺杂剂和p型掺杂剂 。

公开(公告)号：US09082905B2

公开(公告)日：2015-07-14

申请号：US13768037

申请日：2013-02-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Dimitar Trifonov Trifonov

IPC: H01L31/062 ,  H01L31/0236 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/103

CPC classification number: H01L31/02366 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/103

Abstract: A semiconductor device contains a photodiode formed in a substrate of the semiconductor device. At a top surface of the substrate, over the photodiode, a surface grating of periodic field oxide in a periodic configuration and/or gate structures in a periodic configuration is formed. The field oxide may be formed using an STI process or a LOCOS process. A semiconductor device with a surface grating including both field oxide and gate structures has the gate structures over the semiconductor substrate, between the field oxide. The surface grating has a pitch length up to 3 microns. The surface grating covers at least half of the photodiode.

Abstract translation: 半导体器件包含形成在半导体器件的衬底中的光电二极管。 在衬底的顶表面上，在光电二极管上，形成具有周期性构造的周期性场氧化物的表面光栅和/或周期性构造的/或栅极结构。 场氧化物可以使用STI工艺或LOCOS工艺形成。 具有包括场氧化物和栅极结构的表面光栅的半导体器件在半导体衬底之间具有位于场氧化物之间的栅极结构。 表面光栅具有高达3微米的间距长度。 表面光栅覆盖光电二极管的至少一半。

公开(公告)号：US20150145097A1

公开(公告)日：2015-05-28

申请号：US14552995

申请日：2014-11-25

Applicant: Texas Instruments Incorporated

Inventor： Debarshi Basu ,  Henry Litzmann Edwards ,  Dimitar Trifonov Trifonov ,  Josh Du

IPC: H01L31/11 ,  H01L31/02 ,  H01L31/18

CPC classification number: H01L31/1105

Abstract: This invention relates to field photodiodes based on PN junctions that suffer from dark current leakage. An NBL is added to prove a second PN junction with the anode. The second PN junction is reversed biased in order to remove dark current leakage. The present solution requires no additional masks or thin films steps relative to a conventional CMOS process flow.

Abstract translation: 本发明涉及基于PN结的场致电二极管，其具有暗电流泄漏。 添加NBL以证明与阳极的第二PN结。 第二个PN结被反向偏置，以消除暗电流泄漏。 本解决方案不需要相对于常规CMOS工艺流程的附加掩模或薄膜步骤。