公开(公告)号：US10332889B2

公开(公告)日：2019-06-25

申请号：US15951194

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou ,  Ting-Pang Chung ,  Chia-Wei Wu

IPC: H01L21/00 ,  H01L27/108 ,  H01L21/02 ,  H01L21/324 ,  H01L21/48 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.

公开(公告)号：US20180337187A1

公开(公告)日：2018-11-22

申请号：US16028364

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US10068797B2

公开(公告)日：2018-09-04

申请号：US15586240

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US20180226470A1

公开(公告)日：2018-08-09

申请号：US15873913

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

Abstract: A method of fabricating a bottom electrode includes providing a dielectric layer. An atomic layer deposition is performed to form a bottom electrode material on the dielectric layer. Then, an oxidation process is performed to oxidize part of the bottom electrode material. The oxidized bottom electrode material transforms into an oxide layer. The bottom electrode material which is not oxidized becomes a bottom electrode. A top surface of the bottom electrode includes numerous hill-like profiles. Finally, the oxide layer is removed.

公开(公告)号：US10043811B1

公开(公告)日：2018-08-07

申请号：US15627455

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US09728467B2

公开(公告)日：2017-08-08

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/302 ,  H01L29/788 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

公开(公告)号：US09570348B2

公开(公告)日：2017-02-14

申请号：US14709083

申请日：2015-05-11

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu-Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.

Abstract translation: 提供一种形成接触结构的方法。 含硅基板上形成有复合电介质层。 开口穿过复合介电层并暴露出源/漏区的一部分。 在开口中形成氮化钛层，氮化钛层与源极/漏极区域的露出部分接触。 将氮化钛层退火，使得氮化钛层的底部部分转变为硅化钛层。 形成导电层以填充开口。

公开(公告)号：US20160126331A1

公开(公告)日：2016-05-05

申请号：US14554068

申请日：2014-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ju Lee ,  Yao-Chang Wang ,  Nien-Ting Ho ,  Chi-Mao Hsu ,  Kuan-Cheng Su ,  Main-Gwo Chen ,  Hsiao-Kwang Yang ,  Fang-Hong Yao ,  Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。

公开(公告)号：US20150380312A1

公开(公告)日：2015-12-31

申请号：US14314425

申请日：2014-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L21/311

CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂敷抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

公开(公告)号：US20150333142A1

公开(公告)日：2015-11-19

申请号：US14811843

申请日：2015-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first p-work function metal layer, an n-work function metal layer, and a gap-filling metal layer. The second metal gate includes a second p-work function metal layer, the n-work function metal layer, and the gap-filling metal layer. The first p-work function metal layer and the second p-work function metal layer include a same p-typed metal material. A thickness of the first p-work function metal layer is larger than a thickness of the second p-work function metal layer. The first p-work function metal layer, the second p-work function metal layer, and the n-work function metal layer include a U shape.

Abstract translation: 具有金属栅极的半导体器件包括衬底，位于衬底上的第一金属栅极和位于衬底上的第二金属栅极。 第一金属栅极包括第一p功函数金属层，n功函数金属层和间隙填充金属层。 第二金属栅极包括第二功函数金属层，正功函数金属层和间隙填充金属层。 第一功函数金属层和第二功函数金属层包括相同的p型金属材料。 第一功函数金属层的厚度大于第二功函数金属层的厚度。 第一功能金属层，第二功函数金属层和正功函数金属层包括U形。