公开(公告)号：US20140300391A1

公开(公告)日：2014-10-09

申请号：US13858927

申请日：2013-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H03K3/013

CPC classification number: H03K19/00 ,  H01L27/0207 ,  H01L27/0738 ,  H01L27/088 ,  H01L27/092 ,  H03K19/00361

Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.

Abstract translation: 输出缓冲器包括输入/​​输出端，电压源，第一晶体管和第二晶体管。 第一晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第二晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第一晶体管的控制端和第二晶体管的控制端基本上彼此垂直，并且第一晶体管的穿通电压高于第二晶体管的穿通电压。

公开(公告)号：US20250072042A1

公开(公告)日：2025-02-27

申请号：US18376450

申请日：2023-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Hsin Chen ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-cheng Su

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

公开(公告)号：US20210091069A1

公开(公告)日：2021-03-25

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20200343238A1

公开(公告)日：2020-10-29

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

公开(公告)号：US10672759B2

公开(公告)日：2020-06-02

申请号：US16124171

申请日：2018-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

公开(公告)号：US10366978B1

公开(公告)日：2019-07-30

申请号：US16036914

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsiang Chang ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.

公开(公告)号：US20190006348A1

公开(公告)日：2019-01-03

申请号：US16124171

申请日：2018-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

公开(公告)号：US10163895B2

公开(公告)日：2018-12-25

申请号：US15365602

申请日：2016-11-30

Applicant: United Microelectronics Corp.

Inventor： Heng-Yu Lin ,  Kuei-Chih Fan ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40

Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.

公开(公告)号：US20170309613A1

公开(公告)日：2017-10-26

申请号：US15138226

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L27/0277 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/027 ,  H01L27/0274 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41725 ,  H01L29/735

Abstract: A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. The second doped regions, the drain region and the first source region include a second conductivity type complementary to the first conductivity type. The first doped region includes a pair of lateral portions and a pair of vertical portions. The pair of second doped regions is formed under the pair of lateral portions, and the pair of third doped regions is formed under the pair of vertical portions.

公开(公告)号：US09786654B1

公开(公告)日：2017-10-10

申请号：US15298248

申请日：2016-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/87

Abstract: An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and overlapping a portion of the first isolation structure, a source region formed in the substrate at a first side of the gate, and a drain region formed in the substrate at a second side of the gate opposite to the first side. The substrate and the drain region include a first conductivity type, the source region includes a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other.