公开(公告)号：US20140252631A9

公开(公告)日：2014-09-11

申请号：US12794598

申请日：2010-06-04

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L23/52 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.

Abstract translation: 半导体晶片包含多个具有多个接触焊盘的半导体管芯。 牺牲粘合剂沉积在接触垫上。 或者，牺牲粘合剂沉积在载体上。 可以在接触垫之间形成底部填充材料。 单个半导体晶片以分离半导体管芯。 将半导体管芯安装到临时载体上，使得牺牲粘合剂设置在接触垫和临时载体之间。 密封剂沉积在半导体管芯和载体上。 去除载体和牺牲粘合剂以在接触垫上留下通孔。 在密封剂上形成互连结构。 互连结构包括延伸到通孔中以与接触焊盘电连接的导电层。 半导体管芯通过牺牲粘合剂的高度与互连结构偏移。

公开(公告)号：US08791006B2

公开(公告)日：2014-07-29

申请号：US12726880

申请日：2010-03-18

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L21/44 ,  H01L21/20

CPC classification number: H01L28/10 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5228 ,  H01L23/528 ,  H01L24/73 ,  H01L28/40 ,  H01L2224/48463 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Abstract translation: 半导体器件具有形成在聚合物基质复合衬底的第一表面上的第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 在第二绝缘层和第一导电层上形成第二导电层。 第二导电层被卷绕以表现出感应特性。 在第一导电层和第二导电层之间形成第三导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第二导电层上形成凸块。 可以在聚合物基质复合衬底的第二表面上形成第四绝缘层。 或者，可以在形成第一导电层之前，在第一绝缘层上形成第四绝缘层。

公开(公告)号：US20130341784A1

公开(公告)日：2013-12-26

申请号：US13529918

申请日：2012-06-21

Applicant: Yaojian Lin ,  Kang Chen

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2401 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/245 ,  H01L2224/27334 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/92147 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2224/81805 ,  H01L2924/01005

Abstract: A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.

Abstract translation: 半导体器件包括包括第一凸点的球栅阵列（BGA）封装。 第一半导体管芯安装到第一凸块之间的BGA封装。 BGA封装和第一半导体管芯安装在载体上。 第一密封剂沉积在载体上并且围绕BGA封装和第一半导体管芯。 移除载体以暴露第一凸块和第一半导体管芯。 互连结构电连接到第一凸块和第一半导体管芯。 BGA封装还包括基板和安装并电连接到基板的第二半导体管芯。 第二密封剂沉积在第二半导体管芯和衬底上。 第一凸起形成在与第二半导体管芯相对的衬底上。 在BGA封装上形成翘曲平衡层。

公开(公告)号：US08581370B2

公开(公告)日：2013-11-12

申请号：US13349829

申请日：2012-01-13

Applicant: Reza A. Pagaila ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Yaojian Lin

IPC: H01L23/552

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L25/03 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Abstract translation: 半导体器件具有安装到临时载体上的多个半导体管芯。 预制屏蔽框架具有板和从板延伸的整体。 主体在屏蔽框架中限定多个空腔。 可穿透材料沉积在屏蔽框架的空腔中。 屏蔽框架安装在半导体管芯上，使得可穿透材料封装模具。 载体被移除。 在模具，屏蔽框架和可穿透材料上形成互连结构。 屏蔽框架的主体通过互连结构电连接到接地点。 屏蔽框架通过主体或通过板和可穿透材料分离，以分离模具。 TIM与屏蔽框架的板相邻形成在模具上。 散热器安装在屏蔽框架的板上。

公开(公告)号：US08576026B2

公开(公告)日：2013-11-05

申请号：US12331492

申请日：2008-12-10

Applicant: Kai Liu ,  Robert C. Frye ,  Yaojian Lin

Inventor： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC: H01P3/08 ,  H01P7/08

CPC classification number: H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

Abstract translation: 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

公开(公告)号：US08558277B2

公开(公告)日：2013-10-15

申请号：US12831047

申请日：2010-07-06

Applicant: Robert C. Frye ,  Yaojian Lin ,  Rui Huang

Inventor： Robert C. Frye ,  Yaojian Lin ,  Rui Huang

IPC: H01L29/72

CPC classification number: H01L27/0248 ,  H01L23/60 ,  H01L23/64 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/09701 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.

Abstract translation: 半导体器件具有在衬底上形成的集成无源器件（IPD）。 IPD可以是金属 - 绝缘体 - 金属电容器或形成为线圈导电层的电感器。 在衬底的第一侧或背面上形成信号互连结构。 信号互连结构电连接到IPD。 作为静电放电（ESD）保护结构的一部分，在衬底上形成薄膜ZnO层。 薄膜ZnO层具有作为施加到该层的电压的函数的非线性电阻。 导电层形成在衬底上。 薄膜ZnO层电连接在信号互连结构和导电层之间，以提供ESD路径以保护IPD免受ESD瞬变。 在衬底上形成接地互连结构，并将导电层电连接到接地点。

公开(公告)号：US20130249101A1

公开(公告)日：2013-09-26

申请号：US13477982

申请日：2012-05-22

Applicant: Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L21/60 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract translation: 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。

公开(公告)号：US20130154108A1

公开(公告)日：2013-06-20

申请号：US13326128

申请日：2011-12-14

Applicant: Yaojian Lin ,  Kang Chen

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/56 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole.

Abstract translation: 半导体器件具有半导体管芯。 在半导体管芯上形成密封剂。 导电微通孔阵列形成在半导体管芯的覆盖区外部的密封剂上。 通过密封剂形成具有阶梯通孔结构的第一贯通孔，以露出导电微通孔阵列。 在一个实施例中，形成导电微通孔阵列还包括在密封剂和半导体管芯上方形成绝缘层，形成穿过半导体管芯外部的绝缘层的微通孔阵列，并在绝缘层上形成导电层 。 在另一个实施例中，形成导电微通孔阵列还包括形成导电环。 在另一个实施例中，在用于结构支撑的半导体管芯上形成绝缘层，在半导体管芯上形成积聚互连结构，并且在第一通孔内形成导电互连结构。

公开(公告)号：US08445990B2

公开(公告)日：2013-05-21

申请号：US12964810

申请日：2010-12-10

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L27/08

CPC classification number: H01L23/49822 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/20 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00

Abstract: A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Abstract translation: 半导体器件具有形成在载体上的粘合层。 半导体管芯具有在半导体管芯的有效表面上形成的凸块。 半导体管芯安装到载体上，凸起部分地设置在粘合剂层中，以在半导体管芯和粘合剂层之间形成间隙。 密封剂沉积在半导体管芯上并且在半导体管芯和粘合剂层之间的间隙内。 去除载体和粘合剂层以从密封剂露出凸块。 绝缘层形成在密封剂上。 导电层以缠绕构型形成在绝缘层上，以呈现电感性能并与凸点电连接。 导电层部分地设置在半导体管芯的覆盖区内。 由间隙和绝缘层确定的导电层具有与半导体管芯的分离。

公开(公告)号：US08409926B2

公开(公告)日：2013-04-02

申请号：US12720057

申请日：2010-03-09

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng ,  Xusheng Bao

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng ,  Xusheng Bao

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14135 ,  H01L2224/221 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract translation: 多个半导体管芯安装到临时载体上。 密封剂沉积在半导体管芯和载体上。 密封剂的一部分被指定为模具之间的锯道，并且密封剂的一部分被指定为围绕密封剂的周边的基底边缘。 载体被移除。 在模具，锯条和基板边缘上形成第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一导电层和第一绝缘层上形成第二绝缘层。 通过第一绝缘层和锯条将密封剂分离，以分离半导体管芯。 可以在锯条的相对侧的第一绝缘层中形成通道或网状图案，或者第一绝缘层覆盖整个锯条和半导体管芯周围的成型区域。