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    Cache coherence protocol with speculative writestream
    75.
    发明授权
    Cache coherence protocol with speculative writestream 有权
    缓存一致性协议与推测写入

    公开(公告)号：US07376793B2

    公开(公告)日：2008-05-20

    申请号：US11186034

    申请日：2005-07-21

    Applicant: Robert E. Cypher ,  Anders Landin

    Inventor： Robert E. Cypher ,  Anders Landin

    IPC: G06F13/00

    CPC classification number: G06F12/0828 ,  G06F12/0855

    Abstract: A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operation to an entire coherency unit by conveying a WSO request to a home subsystem of the coherency unit. The requester is configured to perform the write operation without first receiving a copy of the coherency unit and complete WSO transactions initiated in the order in which they are initiated. The home subsystem is configured to process multiple WSO transactions directed to a given coherency unit in the order in which they are received. When the requester initiates a WSO transaction to a given coherency unit, the coherency unit is locked. Responsive to receiving the WSO request, the home subsystem conveys a pull request for the write data to the requester. If the requester detects a timeout condition, the requester may cancel the WSO transaction and unlock the coherency unit in the requesting node. The requester may further convey an acknowledgment to the home subsystem indicating no data will be returned. The home subsystem may then treat the WSO transaction as being complete.

    Abstract translation: 一种用于在计算系统中执行推测性写入事务的系统和方法。 包括多个子系统的计算系统具有被配置为通过向一致性单元的归属子系统传送WSO请求来发起写入流顺序（WSO）事务以对整个一致性单元执行写入操作的请求子系统。 请求者被配置为执行写入操作，而不首先接收一致性单元的副本，并以其发起的顺序完成发起的WSO事务。 家庭子系统被配置为按照它们被接收的顺序处理指向给定一致性单元的多个WSO事务。 当请求者向给定的一致性单元发起WSO事务时，一致性单元被锁定。 响应于接收到WSO请求，家庭子系统向请求者传送写入数据的拉取请求。 如果请求者检测到超时条件，则请求者可以取消WSO事务并解除请求节点中的一致性单元。 请求者还可以向家庭子系统发送确认，指示不返回任何数据。 然后，家庭子系统可以将WSO交易视为完成。

    Distributed Cache Coherence at Scalable Requestor Filter Pipes that Accumulate Invalidation Acknowledgements from other Requestor Filter Pipes Using Ordering Messages from Central Snoop Tag
    76.
    发明申请
    Distributed Cache Coherence at Scalable Requestor Filter Pipes that Accumulate Invalidation Acknowledgements from other Requestor Filter Pipes Using Ordering Messages from Central Snoop Tag 有权
    可扩展请求者的分布式缓存一致性累积无效的过滤器来自其他请求者过滤器管道的致谢使用来自中央监听标签的订购消息

    公开(公告)号：US20070186054A1

    公开(公告)日：2007-08-09

    申请号：US11307413

    申请日：2006-02-06

    Applicant: David Kruckemyer ,  Kevin Normoyle ,  Robert Hathaway

    Inventor： David Kruckemyer ,  Kevin Normoyle ,  Robert Hathaway

    IPC: G06F13/28

    CPC classification number: G06F12/082 ,  G06F12/0828

    Abstract: A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation. All ordering, data, and invalidation acknowledgement messages must be received by the requesting filter pipe before loading the data into its cache.

    Abstract translation: 多处理器，多缓存系统具有过滤器管道，其存储发送到中央一致性控制器的请求消息的条目。 中央一致性控制器使用一致性规则对来自过滤器管道的请求进行排序，但不跟踪完成无效。 中央一致性控制器读取窥探标签以识别具有所请求的高速缓存行的副本的共享高速缓存。 中央一致性控制器向请求过滤管发送排序消息。 排序消息具有指示共享缓存数量的无效计数。 每个共享缓存从中央一致性控制器接收到无效消息，使其高速缓存行的副本无效，并向请求的过滤器管道发送无效确认消息。 请求过滤管道减少无效计数，直到所有共享缓存都确认无效。 在将数据加载到其缓存中之前，请求过滤器管道必须接收所有排序，数据和无效确认消息。

    System and method for handling memory requests in a multiprocessor shared memory system
    77.
    发明授权
    System and method for handling memory requests in a multiprocessor shared memory system 有权
    用于处理多处理器共享存储器系统中的存储器请求的系统和方法

    公开(公告)号：US07222222B1

    公开(公告)日：2007-05-22

    申请号：US10601030

    申请日：2003-06-20

    Applicant: Kelvin S. Vartti ,  Ross M. Weber

    Inventor： Kelvin S. Vartti ,  Ross M. Weber

    IPC: G06F12/00

    CPC classification number: G06F12/0828 ,  G06F13/1642

    Abstract: A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a linked list. Only the oldest pending one of these multiple requests is issued to the memory. When data is returned from the memory, the requests are processed in an order determined by the linked list. That is, the data is provided to a processor associated with the oldest request. Thereafter, the data is retrieved and provided to the processor associated with the next request, and so on. A request issued by the memory soliciting the return of the data to the memory may also be added to the linked list to be processed in the foregoing manner.

    Abstract translation: 提供了一种用于跟踪数据处理系统内的存储器请求的系统和方法。 该系统包括一个请求跟踪电路，该电路被耦合以接收来自多个处理器的数据请求。 使用链表跟踪对同一内存地址的多个挂起请求。 只有这些多个请求中的最旧的等待一个发出到内存。 当从存储器返回数据时，以由链表确定的顺序处理请求。 也就是说，将数据提供给与最早请求相关联的处理器。 此后，数据被检索并提供给与下一请求相关联的处理器，等等。 由存储器发出的请求发出的请求也可以以上述方式被添加到链接列表中以被处理。

    System and method for responses between different cache coherency protocols
    78.
    发明授权
    System and method for responses between different cache coherency protocols 有权
    用于不同缓存一致性协议之间的响应的系统和方法

    公开(公告)号：US07177987B2

    公开(公告)日：2007-02-13

    申请号：US10760436

    申请日：2004-01-20

    Applicant: Stephen R. Van Doren ,  Gregory Edward Tierney ,  Simon C. Steely, Jr.

    Inventor： Stephen R. Van Doren ,  Gregory Edward Tierney ,  Simon C. Steely, Jr.

    IPC: G06F12/00 ,  G06F13/00

    CPC classification number: G06F12/0831 ,  G06F12/0828 ,  G06F2212/2542

    Abstract: Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.

    Abstract translation: 公开了用于为不同的高速缓存一致性协议提供响应的系统和方法。 一个实施例可以包括包括采用第一高速缓存一致性协议的第一节点的系统。 与第一节点相关联的检测器基于由第一节点向根据第二高速缓存一致性协议提供的请求提供的响应来检测条件，第二高速缓存一致性协议不同于第一高速缓存一致性协议。 第一节点提供对根据检测器检测到的条件而变化的对第一节点的给定一个请求的响应。

    System and method for conflict responses in a cache coherency protocol with ordering point migration
    80.
    发明申请
    System and method for conflict responses in a cache coherency protocol with ordering point migration 审中-公开
    具有排序点迁移的缓存一致性协议中的冲突响应的系统和方法

    公开(公告)号：US20050160238A1

    公开(公告)日：2005-07-21

    申请号：US10761073

    申请日：2004-01-20

    Applicant: Simon Steely ,  Gregory Tierney ,  Stephen Van Doren

    Inventor： Simon Steely ,  Gregory Tierney ,  Stephen Van Doren

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0828 ,  G06F2212/2542

    Abstract: A system comprises a first node that provides a source broadcast request for data. The first node is operable to respond in a first manner to other source broadcast requests for the data while the source broadcast for the data is pending at the first node. The first node is operable to respond in a second manner to the other source broadcast requests for the data in response to receiving an ownership data response at the first node.

    Abstract translation: 系统包括提供数据的源广播请求的第一节点。 第一节点可操作以以第一种方式响应数据的其他源广播请求，而数据的源广播在第一节点处待定。 第一节点可操作以响应于在第一节点处接收到所有权数据响应，以第二方式响应于数据的其他源广播请求。

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