公开(公告)号：US08722544B2

公开(公告)日：2014-05-13

申请号：US12904609

申请日：2010-10-14

Applicant: Robert K. Barr ,  Raymond Chan

Inventor： Robert K. Barr ,  Raymond Chan

IPC: H01L21/302 ,  H01L21/461 ,  C11D7/32 ,  C25F3/00

CPC classification number: H01L21/30604 ,  H01L21/0201 ,  H01L21/02052 ,  H01L31/18

Abstract: A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.

Abstract translation: 同时从半导体晶片清洗无机和有机污染物并微蚀刻半导体晶片的方法。 在半导体晶片从锭切割或切割之后，它们被切割流体以及来自切割过程中使用的锯的金属和金属氧化物污染。 使用含有碱性化合物和中等范围烷氧基化物的碱性碱性水溶液和微蚀刻溶液来同时清洁和微蚀刻半导体晶片。

公开(公告)号：US20140070381A1

公开(公告)日：2014-03-13

申请号：US13786035

申请日：2013-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuhide DOI ,  Soichi HOMMA ,  Katsuyoshi WATANABE ,  Taku NISHIYAMA ,  Takeshi IKUTA ,  Naohisa OKUMURA

IPC: H01L23/495 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L23/495 ,  G06K19/07732 ,  H01L21/0201 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.

Abstract translation: 半导体存储卡包括具有外部连接端子的引线框架，安装在引线框架上的控制器芯片和安装在引线框架上的存储器芯片。 引线框架，控制器芯片和存储器芯片由具有外部连接端子露出的表面的密封树脂层和围绕外部连接端子的凹部密封。

公开(公告)号：US20130337631A1

公开(公告)日：2013-12-19

申请号：US13525041

申请日：2012-06-15

Applicant: Sen-Hong Syue ,  Pu-Fang Chen ,  Shiang-Bau Wang

Inventor： Sen-Hong Syue ,  Pu-Fang Chen ,  Shiang-Bau Wang

IPC: H01L21/762 ,  C30B15/04

CPC classification number: C30B15/04 ,  C30B15/00 ,  C30B15/203 ,  C30B15/206 ,  C30B15/22 ,  C30B29/06 ,  C30B31/02 ,  C30B31/04 ,  C30B31/165 ,  C30B33/00 ,  H01L21/0201 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/3225 ,  H01L21/76224 ,  H01L29/365 ,  H01L29/78

Abstract: A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

Abstract translation: 提供了一种用于向半导体晶片提供支撑的系统和方法。 一个实施例包括在半导体晶片与半导体晶锭分离之前，在形成半导体晶锭期间引入空位增强材料。 空位增强材料在半导体晶锭内以高密度形成空位，并且在诸如退火的高温过程中，空位形成半导体晶片内的体微小缺陷。 这些大量微缺陷有助于在后续处理过程中提供支撑并加强半导体晶片，并有助于减少或消除否则会发生的指纹叠加。

公开(公告)号：US08587113B2

公开(公告)日：2013-11-19

申请号：US13912907

申请日：2013-06-07

Applicant: Lam Research Corporation

Inventor： Keith William Gaff ,  Keith Comendant ,  Anthony Ricci

IPC: H01L23/48 ,  H01L23/52

CPC classification number: F25B21/04 ,  H01L21/0201 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H01L35/34 ,  Y10T29/49083 ,  Y10T29/49165

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract translation: 在半导体等离子体处理装置中用于衬底支撑组件的热板包括以可伸缩复用布局布置的多个可独立控制的平面热区，以及用于独立地控制和供电平面加热器区的电子装置。 每个平面热区使用至少一个珀耳帖装置作为热电元件。 其中结合有热敏板的基板支撑组件具有静电夹持电极层和温度控制的基板。 用于制造热板的方法包括将具有平面热区域，正，负和公共线路和通孔的陶瓷或聚合物片材结合在一起。

公开(公告)号：US20120164338A1

公开(公告)日：2012-06-28

申请号：US13393682

申请日：2010-09-14

Applicant: Hyo-Jung Roh ,  Dong-Kyu Ju ,  Hyun-Jin Kim ,  Deog-Bae Kim

Inventor： Hyo-Jung Roh ,  Dong-Kyu Ju ,  Hyun-Jin Kim ,  Deog-Bae Kim

IPC: C09D179/00 ,  B05D3/00 ,  C07D251/34

CPC classification number: G03F7/091 ,  B05D3/02 ,  C07D251/06 ,  C08F283/00 ,  C08G75/00 ,  C08K5/0025 ,  C08K5/42 ,  C09D5/006 ,  G03F7/168 ,  H01L21/0201 ,  H01L21/0271 ,  H01L21/4757 ,  H01L31/02168 ,  H01L2924/0705 ,  H01L2924/364 ,  C08L81/00

Abstract: An isocyanurate compound for forming an organic anti-reflective coating layer, which has superior stability and etch rate at a high temperature, and which has a high refractive index, is represented by following Formula 1. In Formula 1, R is independently a hydrogen atom or a methyl group, R1 is independently a chain type or ring type saturated or unsaturated hydrocarbyl group of 1 to 15 carbon atoms containing 0 to 6 of hetero atoms, and R2 independently a chain type or ring type saturated or unsaturated hydrocarbyl group of 1 to 15 carbon atoms containing 0 to 15 of hetero atoms, wherein, R1 can have at least two bonding parts, and in the case that R1 has at least two bonding parts, the rest parts except R1 of the compounds represented by Formula 1 can connect to the R1 to form a polymer structure.

Abstract translation: 用于形成有机抗反射涂层的异氰脲酸酯化合物，其在高温下具有优异的稳定性和蚀刻速率，并且具有高折射率，由下式1表示。在式1中，R独立地为氢原子 或甲基，R 1独立地为含有0〜6个杂原子的1〜15个碳原子的链型或环型饱和或不饱和烃基，R2独立地为1〜1的链型或环型饱和或不饱和烃基 含有0〜15个杂原子的15个碳原子，其中，R1可以具有至少两个键合部分，并且在R1具有至少两个键合部分的情况下，由式1表示的化合物除了R1之外的其余部分可以连接到 R1形成聚合物结构。

公开(公告)号：US20110140214A1

公开(公告)日：2011-06-16

申请号：US12963862

申请日：2010-12-09

Applicant: Tatsuro Takagaki

Inventor： Tatsuro Takagaki

IPC: H01L29/84 ,  H01L23/544 ,  H01L21/68

CPC classification number: H01L27/0207 ,  B81B2201/0235 ,  B81B2203/0136 ,  B81B2207/053 ,  B81C1/00214 ,  G01P15/0802 ,  G01P15/123 ,  G01P15/125 ,  G01P15/18 ,  G01P2015/0814 ,  G01P2015/0842 ,  H01L21/0201 ,  H01L23/544 ,  H01L41/332 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A pattern arrangement method including using a stepper to arrange a plurality of chip patterns arranged parallel to a first direction and a second direction on a silicon wafer using a reticule which includes a plurality of patterns expanded in the first direction and the second direction which intersects the first direction and arranged linearly and intermittently, wherein the stepper adjusts the position of the reticule and the silicon wafer which faces the reticule so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different.

Abstract translation: 一种图案布置方法，包括使用步进器，使用包括沿与所述第一方向和第二方向相交的第一方向和第二方向扩展的多个图案的网格在硅晶片上布置平行于第一方向和第二方向布置的多个芯片图案 第一方向并且线性地和间歇地布置，其中步进器调整面对网状物的网状物和硅晶片的位置，使得其中硅晶片的解理面和在硅晶片上以图案排列的表面相交的轴相交 ，而第一个方向是不同的。

公开(公告)号：US20070082460A1

公开(公告)日：2007-04-12

申请号：US11537023

申请日：2006-09-29

Applicant: Hiroyuki Ishida

Inventor： Hiroyuki Ishida

IPC: H01L21/30 ,  H01L21/46

CPC classification number: B24B9/065 ,  B24C1/086 ,  H01L21/0201 ,  H01L21/02057 ,  H01L21/67051

Abstract: A method of processing a wafer includes a masking process for providing a mask on a surface of a film-formed wafer except for a wafer peripheral portion, and polishing process for spraying a processing liquid containing an inorganic material onto the wafer peripheral portion. According to the method of processing a wafer, it is possible to easily remove impurities existing on a wafer peripheral portion.

Abstract translation: 处理晶片的方法包括用于在除了晶片周边部分之外的成膜晶片的表面上提供掩模的掩模工艺，以及用于将含有无机材料的处理液喷射到晶片周边部分上的抛光工艺。 根据晶片的处理方法，可以容易地除去存在于晶片周边部分上的杂质。

公开(公告)号：US06582280B1

公开(公告)日：2003-06-24

申请号：US09555836

申请日：2000-06-06

Applicant: Toshiaki Otaka ,  Teruaki Fukami

Inventor： Toshiaki Otaka ,  Teruaki Fukami

IPC: B24C1100

CPC classification number: H01L21/0201 ,  B24C11/00 ,  B24C11/005

Abstract: A silicon wafer is sand blasted using a sand blasting abrasive material containing a chelating agent which is selected from the group consisting of, for example, the following compounds (1) to (4) and salts thereof: (1) Nitrilotriacetic acid (NTA) (2) Ethylenediaminetetraacetic acid (EDTA) (3) Diethylenediamine-N,N,N″,N″-pentaacetic acid (DTPA) (4) Cyclohexanediaminetetraacetic acid (CyDTA).

Abstract translation: 使用含有螯合剂的喷砂研磨材料对硅晶片进行喷砂处理，所述螯合剂选自例如以下化合物（1）至（4）及其盐：（1）亚硝酸三乙酸（NTA） （2）乙二胺四乙酸（EDTA）（3）二乙二胺-N，N，N“，N” - 五乙酸（DTPA）（4）环己烷二胺四乙酸（CyDTA）。

公开(公告)号：US12083705B2

公开(公告)日：2024-09-10

申请号：US17414680

申请日：2019-12-12

Applicant: SILTRONIC AG

Inventor： Axel Beyer ,  Stefan Welsch

IPC: B28D5/04 ,  B24B27/06 ,  B28D5/00 ,  H01L21/67 ,  B23D59/00 ,  B28D7/00 ,  H01L21/02

CPC classification number: B28D5/0064 ,  B24B27/0633 ,  B28D5/0082 ,  B28D5/045 ,  H01L21/67092 ,  H01L21/67253 ,  B23D59/00 ,  B28D5/00 ,  B28D5/0058 ,  B28D5/007 ,  B28D5/04 ,  B28D7/00 ,  H01L21/0201

Abstract: Semiconductor wafers are produced from a workpiece by means of a wire saw, by feeding the workpiece through an arrangement of wires tensioned between wire guide rollers and divided into wire groups, the wires moving in a running direction producing kerfs as wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups determined, and for each of the wire groups compensating movements of the wires of the wire group are induced as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.

公开(公告)号：US20230230829A1

公开(公告)日：2023-07-20

申请号：US18147764

申请日：2022-12-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  National University Corporation Tokai National Higher Education and Research System ,  HAMAMATSU PHOTONICS K.K.

Inventor： SHOSUKE NAKABAYASHI ,  JUNJI OHARA ,  MASATAKE NAGAYA ,  CHIAKI SASAOKA ,  SHOICHI ONDA ,  JUN KOJIMA ,  DAISUKE KAWAGUCHI ,  RYUJI SUGIURA ,  TOSHIKI YUI ,  KEISUKE HARA

IPC: H01L21/02

CPC classification number: H01L21/0201

Abstract: A method of manufacturing a semiconductor element includes formation of a modified layer, detection of a first region, and cutting of a semiconductor wafer. In the formation of the modified layer, a laser is irradiated on the semiconductor wafer to form the modified layer extending along a surface of the semiconductor wafer inside the semiconductor wafer. The surface of the semiconductor wafer includes a peripheral portion having the first region and a second region. The first region is a region in which the modified layer is not located, and the second region is a region in which the modified layer is formed. In the cutting of the semiconductor wafer, the semiconductor wafer is cut at the modified layer starting from the second region.