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    Semiconductor device
    72.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08174122B2

    公开(公告)日：2012-05-08

    申请号：US12956333

    申请日：2010-11-30

    Applicant: Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

    Inventor： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

    Abstract translation: 在形成于半导体衬底顶部的绝缘膜上形成沟槽，并且在沟槽的表面上形成阻挡金属膜。 在阻挡金属膜上形成铜或铜合金膜之后，在室温至400℃的范围内形成氧化反应的标准能量为负的氧吸收膜，其中绝对值 的标准形成能量大于形成阻挡金属膜的能量，并且组件在200至400℃的温度范围内被加热。由此可以提供具有高可靠性布线的半导体器件，其中 增加了铜界面对阻挡金属膜的附着力，抑制了界面的铜扩散，防止了电迁移和应力迁移。

    SELF-ALIGNED BARRIER LAYERS FOR INTERCONNECTS
    74.
    发明申请
    SELF-ALIGNED BARRIER LAYERS FOR INTERCONNECTS 有权
    用于互连的自对准障碍层

    公开(公告)号：US20110254164A1

    公开(公告)日：2011-10-20

    申请号：US13051792

    申请日：2011-03-18

    Applicant: Roy G. GORDON ,  Hoon Kim

    Inventor： Roy G. GORDON ,  Hoon Kim

    IPC: H01L23/48 ,  H01L21/283

    CPC classification number: H01L21/76864 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

    Abstract translation: 用于集成电路的互连结构包括在集成电路中完全包围铜线的硅酸锰和锰氮化硅层，以及用于制造其的方法。 硅酸锰形成阻止铜从电线扩散的屏障，从而保护绝缘体不被过早击穿，并保护晶体管免受铜的退化。 硅酸锰和氮化硅锰也促进了铜和绝缘体之间的强粘附，从而在制造和使用期间保持了器件的机械完整性。 铜锰硅酸盐和锰氮化硅界面的强粘附性也可防止在使用设备期间铜的电迁移而导致故障。 含锰护套还可以保护铜免受氧气或水从其周围的腐蚀。

    Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area
    78.
    发明申请
    Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area 有权
    制造在周边区域具有分离的导电图案的半导体晶片装置的方法

    公开(公告)号：US20070010087A1

    公开(公告)日：2007-01-11

    申请号：US11519052

    申请日：2006-09-12

    Applicant: Kenichi Watanabe

    Inventor： Kenichi Watanabe

    IPC: H01L21/4763

    CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

    Abstract translation: 一种制造半导体晶片装置的方法包括以下步骤：（a）在半导体晶片上形成较低的布线图案，所述下布线图案与电路区域中的半导体元件连接; （b）在半导体晶片上形成具有平坦化表面的层间绝缘膜，覆盖下布线图案并具有平坦化表面; 和（c）通过嵌入通孔导体，布线连接到电路区域中连接到下布线图案和配置在通路导体上的布线图案的通孔导体和对应于电路区域以外的周边区域中的布线图案的导体图案 图案和导体图案，导电图案是电隔离的。 该方法可以形成期望的布线结构，并且可以防止有效晶片区域中的有缺陷的器件的百分比的增加。

    Semiconductor device
    80.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07119442B2

    公开(公告)日：2006-10-10

    申请号：US10986071

    申请日：2004-11-12

    Applicant: Sachiyo Ito ,  Masahiko Hasunuma

    Inventor： Sachiyo Ito ,  Masahiko Hasunuma

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/74

    CPC classification number: H01L21/76835 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device comprising a first insulating layer formed above a semiconductor substrate, and comprising a first insulating material, a second insulating material and a hole, a relative dielectric constant of the first insulating material being 3 or less, a Young's modulus of the first insulating material being 10 GPa or less, a linear expansivity of the first insulating material being greater than 30×10−6° C.−1, and a linear expansivity of the second insulating material being 30×10−6° C.−1 or less, and a second insulating layer formed on the first insulating layer, the second insulating layer having a groove connected to the hole, wherein a linear expansivity α of the first insulating layer within 6 μm from the hole is 30×10−6° C.−1 or less, where α = ∑ i = 1 ⁢ v i ⁢ α i , vi and αi are a volume ratio and a linear expansivity of an i-th insulating material.

    Abstract translation: 一种半导体器件，包括在半导体衬底上形成的第一绝缘层，并且包括第一绝缘材料，第二绝缘材料和孔，第一绝缘材料的相对介电常数为3以下，第一绝缘材料的杨氏模量 材料为10GPa或更小，第一绝缘材料的线性膨胀率大于30×10 -6℃。以及第二绝缘材料的线性膨胀性 以及形成在第一绝缘层上的第二绝缘层，第二绝缘层具有连接到孔的凹槽， 其中所述第一绝缘层在距离所述孔6μm内的线性膨胀系数α为30×10 -6℃以下，其中 alpha = Σ 我 = 1 MSUB> / MO> v ，而第i种绝缘材料的体积比和线性膨胀性。

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