公开(公告)号：US20060273069A1

公开(公告)日：2006-12-07

申请号：US11146498

申请日：2005-06-06

Applicant: Nigel Bromley ,  Martin Gouch ,  Christoph Bittner

Inventor： Nigel Bromley ,  Martin Gouch ,  Christoph Bittner

IPC: C23F1/00 ,  B44C1/22 ,  C03C15/00

CPC classification number: H05K3/027 ,  H05K3/061 ,  H05K2201/09363 ,  H05K2203/013 ,  H05K2203/1476 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conductive material around the edge(s) of desired conductive region(s) of the first portion; and laying down an etch resistant material on the conductive layer, the etch resistant material defining a second portion of the conductive pattern, removing conductive material from those areas of the second portion not covered by the etch resistant material, and then removing the etch resistant material.

Abstract translation: 在基板上形成导电图案的方法。 该方法包括提供承载导电层的衬底; 通过将所述导电层暴露于激光来形成所述导电图案的第一部分，并且控制所述激光以去除所述第一部分的所需导电区域的边缘周围的导电材料; 以及在所述导电层上铺设耐蚀刻材料，所述耐蚀刻材料限定所述导电图案的第二部分，从不被所述耐蚀刻材料覆盖的所述第二部分的那些区域去除导电材料，然后去除所述耐蚀刻材料 。

公开(公告)号：US06979898B1

公开(公告)日：2005-12-27

申请号：US09420086

申请日：1999-10-18

Applicant: Warren M. Farnworth ,  Alan G. Wood

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L21/48 ,  H05K3/02 ,  H01L23/04 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/3128 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0218 ,  H05K1/113 ,  H05K3/027 ,  H05K2201/09363 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor component and a method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The semiconductor component includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.

Abstract translation: 提供了一种半导体元件和用于制造诸如印刷电路板，多芯片模块，芯片级封装和测试载体之类的半导体元件的方法。 半导体部件包括提供其上具有覆盖层的导电层的衬底。 使用激光加工工艺，在导电层中形成凹槽以限定衬底上的导体图案。 导体可以形成为期望的尺寸和间隔，并且可以包括诸如接合焊盘，导电通孔和外部球接触的特征。 此外，所选择的导体可以配置为共面接地或电压迹线，用于调整配置为信号迹线的其他导体中的阻抗值。

公开(公告)号：US6107119A

公开(公告)日：2000-08-22

申请号：US110232

申请日：1998-07-06

Applicant: Warren M. Farnworth ,  Alan G. Wood

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L21/48 ,  H05K3/02 ,  H01L21/44 ,  H01L21/50

CPC classification number: H01L23/3128 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H05K1/0218 ,  H05K3/027 ,  G01R1/0483 ,  G01R3/00 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/72 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/113 ,  H05K2201/09363

Abstract: A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.

Abstract translation: 提供了一种用于制造诸如印刷电路板，多芯片模块，芯片级封装和测试载体的半导体部件的方法。 该方法包括提供其上具有覆盖层的导电层的衬底。 使用激光加工工艺，在导电层中形成凹槽以限定衬底上的导体图案。 导体可以形成为期望的尺寸和间隔，并且可以包括诸如接合焊盘，导电通孔和外部球接触的特征。 此外，所选择的导体可以配置为共面接地或电压迹线，用于调整配置为信号迹线的其他导体中的阻抗值。

公开(公告)号：US4486273A

公开(公告)日：1984-12-04

申请号：US520478

申请日：1983-08-04

Applicant: Joseph P. Lutfy ,  Thaddeus J. Grabowski ,  Robert G. Arnold

Inventor： Joseph P. Lutfy ,  Thaddeus J. Grabowski ,  Robert G. Arnold

IPC: C25D5/02 ,  C25D5/54 ,  H05K3/02 ,  H05K3/10 ,  H05K3/24 ,  C25D5/34

CPC classification number: H05K3/241 ,  C25D5/02 ,  C25D5/54 ,  H05K3/108 ,  H05K2201/09363 ,  H05K3/027 ,  Y10S205/918

Abstract: Process for the maskless electroplating of selective areas of a dielectric substrate comprising depositing an electroconductive film on the surface, evaporating a narrow band of the film off the surface to expose a narrow strip of substrate surrounding a zone of the film where electroplating is unwanted, immersing the substrate in an electroplating bath opposite an appropriate anode, and cathodizing only that portion of the film that covers the region sought to be plated. In one embodiment a laser beam is used to selectively evaporate electroless copper from the surface of an ABS substrate.

Abstract translation: 用于对电介质基底的选择性区域进行无掩膜电镀的方法，包括在表面上沉积导电膜，将膜的窄带从表面蒸发，以暴露围绕电镀区不需要的薄膜区域的窄条带，浸渍 在与适当的阳极相对的电镀槽中的衬底，仅阴极化覆盖寻求镀覆的区域的膜的那部分。 在一个实施例中，激光束用于从ABS衬底的表面选择性地蒸发无电解铜。

公开(公告)号：US3610752A

公开(公告)日：1971-10-05

申请号：US3610752D

申请日：1970-01-15

Applicant: ATOMIC ENERGY COMMISSION

Inventor： WILSON FREDERICK C

IPC: G03F1/00 ,  G03F7/20 ,  H05K3/00 ,  G03B41/00

CPC classification number: G03F7/70058 ,  G03F1/00 ,  G03F7/7035 ,  G03F7/70583 ,  H05K3/0002 ,  H05K2201/09363 ,  H05K2203/056

Abstract: An improved process for preparing printed circuit boards in which only the conductor surrounding the circuitry is removed. A refractor is utilized in preparing the circuit board negative to obtain exposure of the film only in the regions directly adjacent the lines representing the circuitry.

公开(公告)号：US20180196326A1

公开(公告)日：2018-07-12

申请号：US15482257

申请日：2017-04-07

Applicant: E INK CORPORATION

Inventor： Richard J. PAOLINI, JR. ,  George G. HARRIS ,  Keith A. JACOBSEN ,  Henry Ware GALE

IPC: G02F1/167 ,  H05K3/04 ,  H05K3/40 ,  H05K3/02 ,  H05K1/11 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: G02F1/167 ,  G02F1/13452 ,  G02F1/136286 ,  G02F2001/136295 ,  H05K3/027 ,  H05K3/12 ,  H05K3/4053 ,  H05K2201/09363 ,  H05K2203/107 ,  H05K2203/166

Abstract: The subject matter presented herein relates to a method for producing a backplane for electro-optic displays. The method may include providing a substrate coated with a first conductive material on a first side and a second conductive material on a second side, the second side being positioned opposite from the first side, patterning the first conductive material by cutting through the first conductive material, wherein the patterning of the first conductive material creates electrical isolated conductive segments to be controlled by a driver circuit and creating a plurality of vias on the substrate, the plurality of vias extending through the substrate and providing electrical conductivity between the first and second sides. The method may further include creating a plurality of conductive traces on the second side of the substrate by patterning the second conductive material by locally align the vias to the driver circuit.

公开(公告)号：US09786331B1

公开(公告)日：2017-10-10

申请号：US15220175

申请日：2016-07-26

Applicant: Western Digital Technologies, Inc.

Inventor： Albert John Wallash

IPC: G11B33/14 ,  H05K1/02 ,  G06F1/18

CPC classification number: G11B33/1493 ,  G06F1/182 ,  H01P1/2039 ,  H01P3/026 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/0715 ,  H05K2201/09309 ,  H05K2201/09363 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2201/10242 ,  H05K2201/2072

Abstract: The present disclosure generally relates to a shielded three-layer patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. To reduce costs, PCBs are being made with only four total layers separated by dielectric material. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded three-layer patterned ground structure, not only is the cost reduced, but so is the common mode current and the magnitude of EMI noise, all without any negative impact to the differential signal.

公开(公告)号：US20170141276A1

公开(公告)日：2017-05-18

申请号：US15417373

申请日：2017-01-27

Applicant: NICHIA CORPORATION

Inventor： Motokazu YAMADA ,  Tadaaki MIYATA ,  Naoki MORI

IPC: H01L33/56 ,  H01L33/32 ,  F21S4/22 ,  H01L33/50 ,  H01L33/60 ,  H01L33/62 ,  H01L25/075 ,  H01L33/48

CPC classification number: H01L33/56 ,  F21S4/22 ,  F21Y2101/00 ,  F21Y2103/00 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L27/15 ,  H01L33/32 ,  H01L33/483 ,  H01L33/507 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: A light emitting device includes a substrate, a light emitting element and a sealing resin member. The substrate includes a flexible base, a plurality of wiring portions and a groove portion. The groove portion is formed between the plurality of wiring portions spaced apart from each other, and includes a first groove portion, a second groove portion, and a third groove portion extending in a direction intersecting the first and second groove portions. The first and third groove portions are connected to each other with a curve. The second and third groove portions are connected to each other with a curve. The sealing resin member seals the light emitting element and the substrate. The sealing resin member is arranged on the third groove portion and spaced apart from the first groove portion and the second groove portion.

公开(公告)号：US09474161B2

公开(公告)日：2016-10-18

申请号：US14933616

申请日：2015-11-05

Applicant: Taiwan Green Point Enterprises Co., Ltd.

Inventor： Sheng-Hung Yi ,  Pen-Yi Liao

IPC: H01B13/00 ,  H05K3/00 ,  C23C18/16 ,  C25D5/02 ,  H05K3/18 ,  B23K26/36 ,  B23K26/40 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D7/12 ,  C25F5/00 ,  H05K3/06 ,  H05K3/46 ,  C25D5/54 ,  C23C18/20 ,  H05K3/24 ,  H05K3/02 ,  H05K3/10

CPC classification number: H05K3/0026 ,  B23K26/362 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  C23C18/1603 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/2013 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D5/02 ,  C25D5/54 ,  C25D7/12 ,  C25F5/00 ,  H05K3/0041 ,  H05K3/027 ,  H05K3/067 ,  H05K3/107 ,  H05K3/185 ,  H05K3/24 ,  H05K3/4661 ,  H05K2201/09036 ,  H05K2201/09363 ,  H05K2203/0392 ,  H05K2203/107 ,  Y10T29/49155

Abstract: A circuit substrate includes: an insulative substrate formed with a pattern of a recess, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer disposed within the recess, formed on the bottom wall surface of the recess-defining wall, and spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating; and a primary metal layer plated on the patterned metallic layer structure.

Abstract translation: 电路基板包括：形成有凹槽图案的绝缘基板，所述凹部由凹口限定壁限​​定，所述凹槽限定壁具有从所述底壁表面向上延伸的底壁表面和周围壁表面; 图案化的金属层结构，其至少包括设置在凹部内的图案化的有源金属层，形成在凹陷限定壁的底壁表面上，并且与凹陷限定壁的周围壁表面间隔开，图案化的活性金属 含有能够引发化学镀的活性金属的层; 以及镀在图案化金属层结构上的主金属层。

公开(公告)号：US20160057865A1

公开(公告)日：2016-02-25

申请号：US14933616

申请日：2015-11-05

Applicant: Taiwan Green Point Enterprises Co., Ltd.

Inventor： Sheng-Hung YI ,  Pen-Yi LIAO

IPC: H05K3/00 ,  B23K26/402 ,  C25D3/12 ,  C25D3/38 ,  H05K3/46 ,  C25D3/48 ,  C25D7/12 ,  C25F5/00 ,  H05K3/02 ,  H05K3/06 ,  B23K26/362 ,  C25D3/46

CPC classification number: H05K3/0026 ,  B23K26/362 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  C23C18/1603 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/2013 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D5/02 ,  C25D5/54 ,  C25D7/12 ,  C25F5/00 ,  H05K3/0041 ,  H05K3/027 ,  H05K3/067 ,  H05K3/107 ,  H05K3/185 ,  H05K3/24 ,  H05K3/4661 ,  H05K2201/09036 ,  H05K2201/09363 ,  H05K2203/0392 ,  H05K2203/107 ,  Y10T29/49155

Abstract: A circuit substrate includes: an insulative substrate formed with a pattern of a recess, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer disposed within the recess, formed on the bottom wall surface of the recess-defining wall, and spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating; and a primary metal layer plated on the patterned metallic layer structure.

Abstract translation: 电路基板包括：形成有凹槽图案的绝缘基板，所述凹部由凹口限定壁限​​定，所述凹槽限定壁具有从所述底壁表面向上延伸的底壁表面和周围壁表面; 图案化的金属层结构，其至少包括设置在凹部内的图案化的有源金属层，形成在凹陷限定壁的底壁表面上，并且与凹陷限定壁的周围壁表面间隔开，图案化的活性金属 含有能够引发化学镀的活性金属的层; 以及镀在图案化金属层结构上的主金属层。