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1.
公开(公告)号:US20240222245A1
公开(公告)日:2024-07-04
申请号:US18455553
申请日:2023-08-24
Applicant: Zhuhai ACCESS Semiconductor Co., LTD.
Inventor: Xianming CHEN , Gao HUANG , Yejie HONG , Wenjian LIN , Benxia HUANG , Zhijun ZHANG
IPC: H01L23/498 , H01L21/48 , H05K1/02 , H05K1/18
CPC classification number: H01L23/49822 , H01L21/4857 , H05K1/0298 , H05K1/182 , H05K2201/10242
Abstract: A method for manufacturing embedded device packaging substrate, a packaging substrate, and a semiconductor are disclosed. The method includes: forming a first circuit layer; laminating a first photosensitive layer onto the first circuit layer; providing an embedded device on the first photosensitive layer, with a pin face of the embedded device facing away from the first photosensitive layer; providing a second photosensitive layer covering the embedded device; partially removing the first dielectric layer such that a minimum thickness of the first dielectric layer covering a side surface of the embedded device is greater than or equal to a preset threshold; providing a second dielectric layer covering the first dielectric layer; and forming, on the second dielectric layer, a second circuit layer that is electrically connected to the first circuit layer and the embedded device.
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公开(公告)号:US20240040691A1
公开(公告)日:2024-02-01
申请号:US18212863
申请日:2023-06-22
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Kwon Su YUN
CPC classification number: H05K1/0296 , H05K1/115 , H05K3/02 , H05K2201/10984 , H05K2201/10242 , H05K2201/10674
Abstract: A printed circuit board (PCB) includes an insulating layer, a first solder resist layer disposed on an upper surface of the insulating layer, a first conductive pattern disposed on the insulating layer and providing a conductive post protruding from an upper surface of the first solder resist layer, and a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than the upper surface of the insulating layer.
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公开(公告)号:US20230209717A1
公开(公告)日:2023-06-29
申请号:US18173320
申请日:2023-02-23
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor: Yatao LV , Qingguo TANG , Ning WANG
CPC classification number: H05K1/181 , H05K3/28 , H05K2201/10242
Abstract: Embodiments of this application disclose a packaging module and an electronic device. Both a first surface and a second surface of a PCB in the packaging module are covered with a molding layer, a conductive pin is electrically connected to the PCB, the conductive pin is packaged inside the molding layer along a stacking direction of the PCB and the molding layer, and the conductive pin is partially exposed on an outer surface of the molding layer. When the packaging module performs electrical interaction with another element, the PCB outputs or inputs an electrical signal by using the conductive pin. In this way, there is no need to reserve a through hole on a packaging side of the packaging module, the packaging module may be arranged at a position close to a chip, and there are short wires between the packaging module and the chip.
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公开(公告)号:US20190244877A1
公开(公告)日:2019-08-08
申请号:US16384494
申请日:2019-04-15
Applicant: Cisco Technology, Inc.
Inventor: Phil Slight , Vic Chia
CPC classification number: H01L23/4006 , H01L2023/4062 , H01L2023/4081 , H01L2023/4087 , H05K1/0203 , H05K1/0209 , H05K7/2049 , H05K2201/066 , H05K2201/10242 , H05K2201/10265 , H05K2201/10393 , H05K2201/10409
Abstract: A circuit board includes a heatsink configured to be coupled to the circuit board via a first coupling mechanism, the first coupling mechanism providing an asymmetrical downward force for coupling the heatsink to the circuit board. The circuit board further includes a second coupling mechanism configured to provide a counter force to the asymmetrical downward force of the first coupling mechanism. The counter force can be configured on an overhang portion of the heatsink that does not cover a circuit on the circuit board.
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公开(公告)号:US20190190110A1
公开(公告)日:2019-06-20
申请号:US16272834
申请日:2019-02-11
Applicant: Cambium Networks Limited
Inventor: Paul Clark , Peter Strong , Carl Morrell , Adam Wilkins , Nigel Jonathan Richard King
CPC classification number: H01P3/081 , H01P5/028 , H05K1/0237 , H05K2201/09209 , H05K2201/10242
Abstract: A radio frequency transmission arrangement comprises a ground plate having an aperture comprising a slot with an elongate cross-section and substantially parallel sides, and a first and second transmission line. The thickness of the ground plate is greater than a width of the slot. The aperture is partially filled with a solid dielectric material and partially filled with air. The first transmission line comprises a first elongate conductor on a first side of the ground plate and has an end terminated with a first termination stub. The second transmission line comprises a second elongate conductor on the opposite side of the ground plate and has an end terminated with a second termination stub. The first transmission line is arranged to cross the slot at a point adjacent to the first termination stub, and the second transmission line is arranged to cross the slot at a point adjacent to the second termination stub.
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公开(公告)号:US20180160547A1
公开(公告)日:2018-06-07
申请号:US15806385
申请日:2017-11-08
Applicant: FUJITSU LIMITED
Inventor: Norikazu Ozaki , Hiroshi MIYAO , Satoru HASEGAWA
CPC classification number: H05K1/115 , H05K3/0047 , H05K3/306 , H05K3/4046 , H05K3/4084 , H05K3/42 , H05K2201/10242 , H05K2201/10303 , H05K2201/10401 , H05K2201/10409 , H05K2203/0278
Abstract: A first through hole is formed in a base, a conductive layer covering an inner wall side surface of the first through hole is formed, a columnar electric conductor having a Vickers hardness of a value in a range of 30 Hv or more and 400 Hv or less is inserted into the first through hole formed with the conductive layer, pressure is applied in a vertical direction to the columnar electric conductor, and a second through hole is formed in the columnar electric conductor.
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公开(公告)号:US20180160533A1
公开(公告)日:2018-06-07
申请号:US15369822
申请日:2016-12-05
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor: Ting-Hao LIN , Chiao-Cheng CHANG , Yi-Nong LIN
CPC classification number: H05K3/4641 , H05K3/4647 , H05K3/4682 , H05K2201/10242 , H05K2203/041 , H05K2203/0568
Abstract: A multilayer printed circuit board includes a first circuit board, a second circuit board and bonding films. The first circuit board includes a first dielectric layer, a first wiring pattern layer, a plurality of conductive blocks and a plurality of solder balls. The first wiring pattern layer is formed on a first surface of the first dielectric layer and the conductive blocks are formed on a second surface of the first dielectric layer. The solder balls are formed on a surface of the first wiring pattern layer. The second circuit board includes a second dielectric layer, a second wiring pattern layer, second conductive blocks and conductive pillars. The second wiring pattern layer is formed on a third surface of the second dielectric layer and the second conductive blocks are formed on a fourth surface thereof. The conductive pillars are formed on the second wiring pattern layer.
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8.
公开(公告)号:US09942975B2
公开(公告)日:2018-04-10
申请号:US14875222
申请日:2015-10-05
Applicant: Raytheon Company
Inventor: James M. Elliott , James S. Wilson , David E. Swernofsky
CPC classification number: H05K1/0204 , H05K1/0209 , H05K1/142 , H05K3/301 , H05K2201/066 , H05K2201/10242
Abstract: An apparatus includes a printed circuit board (PCB) including a surface that has a layer of circuitry. The apparatus also includes a heat sink configured to receive heat from the PCB. The apparatus further includes a thermally-conductive post configured to remove the heat from the PCB to the heat sink via thermal conduction through a thermal path. The thermal path is substantially orthogonal to the surface of the PCB. The post includes an end configured to physically couple to the layer of circuitry.
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公开(公告)号:US20180081481A1
公开(公告)日:2018-03-22
申请号:US15712070
申请日:2017-09-21
Applicant: Apple Inc.
Inventor: Douglas G. FOURNIER , James R. KROGDAHL , Daniel W. JARVIS , Edward S. HUO , Lee E. HOOTON , Srikanth V. THIRUPPUKUZHI , Garrett R. OWOC , Michael NGO , David A. PAKULA , Robert F. MEYER
IPC: G06F3/041 , G02F1/1333 , G02F1/1343
CPC classification number: H05K7/20481 , B32B2307/302 , B32B2457/20 , G06F1/1637 , G06F1/1643 , G06F3/0412 , G06F3/0414 , G06F3/044 , G06F2203/04112 , H01M2/08 , H01M2/1016 , H01M2/1022 , H01M2220/30 , H02J7/0042 , H05K1/0216 , H05K1/144 , H05K1/148 , H05K7/20963 , H05K9/0033 , H05K2201/042 , H05K2201/10242 , H05K2201/10257
Abstract: An electronic device having a display assembly is disclosed. Several layers may combine to form the display assembly. For example, the display assembly may include a touch sensitive layer (or touch detection layer), a display layer that present visual information, and a force sensitive layer (or force detection layer). The display layer may include a bend or curve that allows a portion of the display layer to bend around the force sensitive layer. Also, the connectors (that provide electrical and mechanical connections) may be positioned at different locations of the layers. For example, the display layer may include a connector on a first edge region, and the force sensitive layer may include a connector on a second edge region that is perpendicular, or at least substantially perpendicular, to the first edge region. By positioning the connectors on perpendicular edge regions, the display assembly may reduce its footprint.
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公开(公告)号:US20180014426A1
公开(公告)日:2018-01-11
申请号:US15358742
申请日:2016-11-22
Applicant: Ku Yong KIM
Inventor: Ku Yong KIM
CPC classification number: H05K7/205 , H05K1/0204 , H05K1/144 , H05K1/181 , H05K1/182 , H05K3/4608 , H05K5/0008 , H05K7/20472 , H05K2201/0367 , H05K2201/041 , H05K2201/042 , H05K2201/09063 , H05K2201/09854 , H05K2201/1003 , H05K2201/10242
Abstract: A PCB module having a multi-surface heat dissipation structure is provided. The PCB module includes: a multi-layer PCB assembly which includes a heat dissipation plate having electrical insulating properties, and an upper PCB and a lower PCB attached to a top surface and a bottom surface of the heat dissipation plate, respectively; an upper case for covering a top surface of the multi-layer PCB assembly; and a lower case for covering a bottom surface of the multi-layer PCB assembly, and the heat dissipation plate includes; a first heat pole which is thermally in contact with an electronic circuit element mounted on the upper PCB or the lower PCB; and a second heat pole which is thermally in contact with an inner surface of at least one of the upper and lower cases.
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