Abstract:
A part of a tube, through which a fluid passes, is cooled by means of an electronic cooling element and a flow rate of the fluid is measured on the basis of a temperature of a surface of the tube cooled. Not only can the flow rate of the liquid flowing through the tube be determined in a noncontacting manner and a very small flow rate of the liquid be determined, but also the tube is cooled so that no bubbles are generated, and thus the measurement of the liquid, which is apt to generate gases, such as low boiling point liquid, is possible. In addition, the measurement is not influenced by the gases dissolved in the liquid and merely the temperature difference resulting from the flow of the fluid, that is, the rise of the temperature of the fluid, is detected to prevent the measurement from being influenced by the installing posture of the flow meter, so that a highly accurate measurement is possible. Consequently, stable and sure controlling flow rate of liquid is possible.
Abstract:
A control valve in which a surface of a valve seat closer to a valve body is formed so as to be flat. A valve head corresponding to an annularly formed fluid-communication passage is provided with an annular inner convex projection and an annular outer convex projection. These projections engage with the flat surface of the valve seat on the inner side and the outer side of the fluid-communicating passage, respectively. The valve head is provided with a communicating passage for providing communication between a valve body-driving portion side thereof and a valve seat surface side containing the inner convex projection.
Abstract:
A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.
Abstract:
A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table.
Abstract:
Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells should be estimated. If a new read level should be estimated the new read level is calculated as a function of an initial read level and a dwell time and a number of program/erase cycles. A controller provides one or more programming commands representative of the new read level voltage to the memory circuit to read the cells.
Abstract:
The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory controller is configured to divide the flash memory into virtual segments, each segment including blocks of flash memory cells. The controller is also configured to receive a write request to a location designated by a memory identifier and to map the memory identifier to a segment. When the segment matches an open segment and an open block can store the data, the controller is configured to retrieve the open segment and the open block from a collection tracking open blocks and to write the data to the open block. When the segment is different from the open segment, the controller is configured to close the open block, to write the data to a block in the segment, and to update the collection with the block in the segment.
Abstract:
Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command.
Abstract:
Systems and methods for managing key-value stores are disclosed. In some embodiments, the systems and methods may be realized as a method for managing a key-value store including creating an uncompressed tree of key-value pairs, monitoring the growth of the uncompressed tree, compressing the uncompressed tree when the uncompressed tree meets and/or exceeds a specified threshold, and creating a new empty uncompressed tree.
Abstract:
A method for calibrating read levels in a flash memory device is provided. The method includes receiving read information from flash memory in response to a read command, assigning soft information to the received read information, determining an error signal based on the assigned soft information, determining a read level offset based on the error signal, and adjusting a read level in the flash memory by the determined read level offset.
Abstract:
Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.