公开(公告)号：US08889539B2

公开(公告)日：2014-11-18

申请号：US12332877

申请日：2008-12-11

Applicant: Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

Inventor： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

IPC: H01L21/302 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L29/66621

Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Abstract translation: 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

公开(公告)号：US08665405B2

公开(公告)日：2014-03-04

申请号：US13072962

申请日：2011-03-28

Applicant: Yeo-Geon Yoon ,  Hyoung-Wook Lee ,  Mi-Ae Lee ,  Ho-Jun Lee

Inventor： Yeo-Geon Yoon ,  Hyoung-Wook Lee ,  Mi-Ae Lee ,  Ho-Jun Lee

IPC: G02F1/1343 ,  G02F1/136

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1248

Abstract: A thin film transistor array panel includes an insulating substrate, a plurality of pixel electrodes arranged on the insulating substrate in rows and columns, a plurality of thin film transistors connected with the plurality of pixel electrodes, respectively, and a plurality of gate lines and a plurality of data lines connected with the plurality of thin film transistors. When one data line and one pixel electrode which are connected with a single thin film transistor are referred to as a connected data line and a connected pixel electrode, respectively, the plurality of thin film transistors are positioned on a same side of the connected data line in two adjacent rows, and on alternating sides of the connected data line in every other two adjacent rows. Two boundary lines of the connected pixel electrode are overlapped with the connected data line.

Abstract translation: 薄膜晶体管阵列面板包括绝缘基板，以行和列布置在绝缘基板上的多个像素电极，分别与多个像素电极连接的多个薄膜晶体管，以及多个栅极线和 多个数据线与多个薄膜晶体管连接。 将与单个薄膜晶体管连接的一个数据线和一个像素电极分别称为连接的数据线和连接的像素电极时，多个薄膜晶体管位于连接的数据线的同一侧 在两个相邻的行中，并且在每隔一个两个相邻行中连接的数据线的交替侧。 连接的像素电极的两条边界线与连接的数据线重叠。

公开(公告)号：US08450129B2

公开(公告)日：2013-05-28

申请号：US13231225

申请日：2011-09-13

Applicant: Hong-Kee Chin ,  Sang-Gab Kim ,  Woong-Kwon Kim ,  Yong-Mo Choi ,  Seung-Ha Choi ,  Shin-Il Choi ,  Ho-Jun Lee ,  Jung-Suk Bang ,  Yu-Gwang Jeong

Inventor： Hong-Kee Chin ,  Sang-Gab Kim ,  Woong-Kwon Kim ,  Yong-Mo Choi ,  Seung-Ha Choi ,  Shin-Il Choi ,  Ho-Jun Lee ,  Jung-Suk Bang ,  Yu-Gwang Jeong

IPC: H01L33/16

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US20130095858A1

公开(公告)日：2013-04-18

申请号：US13589714

申请日：2012-08-20

Applicant: Ho-jun Lee ,  Yong-gook Park ,  Tae-young Kang ,  Hee-chul Jeon

Inventor： Ho-jun Lee ,  Yong-gook Park ,  Tae-young Kang ,  Hee-chul Jeon

IPC: H04W64/00

CPC classification number: H04W48/16 ,  H04W4/029

Abstract: A method and apparatus for providing a position-based service is provided. The method includes detecting a current position; determining whether the current position is included in a previously set area-of-interest; and scanning for a wireless transceiver in response to a determination that the current position is included in the set area-of-interest.

Abstract translation: 提供了一种用于提供基于位置的服务的方法和装置。 该方法包括检测当前位置; 确定当前职位是否包括在先前设定的兴趣领域中; 以及响应于确定当前位置被包括在所设置的感兴趣区域中来扫描无线收发器。

公开(公告)号：US08119229B2

公开(公告)日：2012-02-21

申请号：US12452613

申请日：2008-07-11

Applicant: Jang-Yeon Hwang ,  Dong-Ryul Kim ,  Gi-Cheul Kim ,  Sang-Uk Ryu ,  Ho-Jun Lee ,  Eun-Sil Lee, legal representative ,  Seung-Lac Ma ,  Myeong-Geun Ko

Inventor： Jang-Yeon Hwang ,  Dong-Ryul Kim ,  Gi-Cheul Kim ,  Sang-Uk Ryu ,  Ho-Jun Lee ,  Seung-Lac Ma ,  Myeong-Geun Ko

IPC: B32B7/02

CPC classification number: C23C14/10 ,  C23C14/081 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/26

Abstract: The present invention provides a multiple layer that comprises two or more first inorganic material layers; and one or more second inorganic material layers that are positioned between the two first inorganic material layers and have the thickness of less than 5 nm, in which the first inorganic material layer is formed of one or more materials that are selected from silicon oxides, silicon carbide, silicon nitride, aluminum nitride and ITO, and the second inorganic material layer is formed of one or more materials that are selected from magnesium, calcium, aluminum, gallium, indium, zinc, tin, barium, and oxides and fluorides thereof, a multiple film that comprises the multiple layer, and an electronic device that comprises the multiple film.

Abstract translation: 本发明提供一种包含两个或更多个第一无机材料层的多层; 以及位于所述两个第一无机材料层之间且具有小于5nm的厚度的一个或多个第二无机材料层，其中所述第一无机材料层由选自氧化硅，硅中的一种或多种材料形成 碳化物，氮化硅，氮化铝和ITO，第二无机材料层由选自镁，钙，铝，镓，铟，锌，锡，钡及其氧化物和氟化物的一种或多种材料形成， 包括多层的多层膜，以及包括该多层膜的电子器件。

公开(公告)号：US20110287233A1

公开(公告)日：2011-11-24

申请号：US13130015

申请日：2009-11-19

Applicant: Seung-Lac Ma ,  Dong-Ryul Kim ,  Gi-Cheul Kim ,  Sang-Uk Ryu ,  Ho-Jun Lee ,  Eun-Sil Lee ,  Jang-Yeon Hwang

Inventor： Seung-Lac Ma ,  Dong-Ryul Kim ,  Gi-Cheul Kim ,  Sang-Uk Ryu ,  Ho-Jun Lee ,  Eun-Sil Lee ,  Jang-Yeon Hwang

IPC: B32B3/00 ,  B32B27/36 ,  B32B13/12 ,  B32B27/00 ,  B32B27/38 ,  B32B7/02 ,  B32B9/04 ,  B32B27/06

CPC classification number: B32B27/08 ,  B32B7/12 ,  B32B27/18 ,  B32B27/281 ,  B32B27/286 ,  B32B27/308 ,  B32B27/32 ,  B32B27/36 ,  B32B27/365 ,  B32B27/38 ,  B32B27/42 ,  B32B2250/40 ,  B32B2264/10 ,  B32B2270/00 ,  B32B2307/306 ,  B32B2307/7242 ,  B32B2307/734 ,  B32B2457/00 ,  B32B2457/202 ,  C08J7/123 ,  G02F2001/133302 ,  Y10T428/24802 ,  Y10T428/24975 ,  Y10T428/26 ,  Y10T428/31504 ,  Y10T428/31507 ,  Y10T428/31511 ,  Y10T428/31721 ,  Y10T428/31786

Abstract: The present invention provides a multilayered plastic substrate that simultaneously satisfies improvement in high temperature thermal deformation according to low linear expansion coefficient and excellent dimensional stability and excellent gas barrier property, and is capable of being used instead of a glass substrate that has brittleness and heavy disadvantages without a problem caused by a difference in linear expansion coefficient between layers, and a method for manufacturing the same.

Abstract translation: 本发明提供一种多层塑料基板，其同时满足根据低线性膨胀系数的高温热变形的改善和优异的尺寸稳定性和优异的阻气性，并且能够用于代替具有脆性和重要缺点的玻璃基板 没有由层之间的线膨胀系数的差异引起的问题及其制造方法。

公开(公告)号：US20110129953A1

公开(公告)日：2011-06-02

申请号：US12955222

申请日：2010-11-29

Applicant: Yong-Jin Kim ,  Dong-Kun Lee ,  Doo-Soo Kim ,  Ho-Jun Lee ,  Kye-Jin Lee

Inventor： Yong-Jin Kim ,  Dong-Kun Lee ,  Doo-Soo Kim ,  Ho-Jun Lee ,  Kye-Jin Lee

IPC: H01L33/32 ,  H01L21/20

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02658 ,  H01L33/007 ,  H01L33/0079

Abstract: A method of manufacturing a nitride semiconductor device is disclosed. The method includes forming a gallium nitride (GaN) epitaxial layer on a first support substrate, forming a second support substrate on the GaN epitaxial layer, forming a passivation layer on a surface of the other region except for the first support substrate, etching the first support substrate by using the passivation layer as a mask, and removing the passivation layer and thereby exposing the second support substrate and the GaN epitaxial layer.

Abstract translation: 公开了一种制造氮化物半导体器件的方法。 该方法包括在第一支撑衬底上形成氮化镓（GaN）外延层，在GaN外延层上形成第二支撑衬底，在除第一支撑衬底之外的另一个区域的表面上形成钝化层，蚀刻第一衬底 通过使用钝化层作为掩模来支撑衬底，以及去除钝化层，从而暴露第二支撑衬底和GaN外延层。

公开(公告)号：US07915698B2

公开(公告)日：2011-03-29

申请号：US12002338

申请日：2007-12-14

Applicant: Doo-Soo Kim ,  Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee

Inventor： Doo-Soo Kim ,  Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee

IPC: H01L29/82

CPC classification number: H01L21/02658 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/0254

Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses on the base substrate that become larger from a central portion of the base substrate towards a peripheral portion when growing a nitride semiconductor film. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.

Abstract translation: 氮化镓半导体衬底及其制造方法技术领域本发明涉及氮化镓衬底等氮化物半导体衬底及其制造方法。 本发明在基底基板的下表面上形成多个沟槽，其构造成在生长氮化物半导体膜时吸收或减小从基底基板的中心部分朝向周边部分变大的基底基板上的应力。 也就是说，本发明在基底基板的下表面上形成沟槽，使得间距变得较小，或者宽度或深度从基底基板的中心部朝向周边部分变大。

公开(公告)号：US20100240790A1

公开(公告)日：2010-09-23

申请号：US12681340

申请日：2008-10-02

Applicant: Sang-Uk Ryu ,  Dong-Ryul Kim ,  Gi-Cheul Kim ,  Ho-Jun Lee ,  Jang-Yeon Hwang ,  Seung-Lac Ma ,  Myeong-Geun Ko

Inventor： Sang-Uk Ryu ,  Dong-Ryul Kim ,  Gi-Cheul Kim ,  Ho-Jun Lee ,  Jang-Yeon Hwang ,  Seung-Lac Ma ,  Myeong-Geun Ko

IPC: C08F2/46 ,  C08F222/40

CPC classification number: C08F283/01 ,  C08K5/3415 ,  C08F222/40 ,  C08L67/03

Abstract: The present invention provides a curing composition comprising maleimide and polyarylate having double bonds and a cured product prepared by using the same. The curing composition according to the present invention is used to provide a cured product having excellent heat-resistance and toughness.

Abstract translation: 本发明提供了包含具有双键的马来酰亚胺和多芳基化合物的固化组合物和通过使用它们制备的固化产物。 本发明的固化组合物用于提供耐热性和韧性优异的固化物。

公开(公告)号：US20100156744A1

公开(公告)日：2010-06-24

申请号：US12655058

申请日：2009-12-21

Applicant: Ho-Jun Lee

Inventor： Ho-Jun Lee

IPC: H01Q1/38 ,  H01P11/00 ,  H01Q1/48

CPC classification number: H01Q1/40 ,  H01Q1/2225 ,  H01Q1/38 ,  H01Q23/00 ,  Y10T29/49016 ,  Y10T29/49018

Abstract: There are provided an antenna using a buildup structure and a method of manufacturing the same. In the antenna, a tag chip is positioned within a dielectric and is connected to a radiator through a connection line or a via-hole, thereby being strong against external environments, decreasing a defective rate and enabling to be used for the special purpose of being positioned within a metal or liquid.

Abstract translation: 提供了使用积层结构的天线及其制造方法。 在天线中，标签芯片位于电介质内，并通过连接线或通孔连接到散热器，从而对外界环境强，降低故障率，并可用于特殊目的 位于金属或液体内。