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    Method and System for Indoor Multipath Ghosts Recognition
    81.
    发明申请
    Method and System for Indoor Multipath Ghosts Recognition 有权

    公开(公告)号：US20240404273A1

    公开(公告)日：2024-12-05

    申请号：US18796196

    申请日：2024-08-06

    Applicant: Imec vzw ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Ruoyu Feng ,  Andre Bourdoux ,  Hichem Sahli ,  Sofie Pollin

    IPC: G06V20/00 ,  G01S13/72 ,  G01S13/89 ,  G06T7/277

    Abstract: A method is provided for indoor multipath ghosts recognition for a multiple-input-multiple-output radar with collocated antennas. The method includes the step of generating a two-dimensional Range-Doppler map for N number of consecutive radar data frames. The method further includes the step of applying a temporal clustering algorithm to the N number of consecutive radar data frames. Moreover, the method includes the step of applying a linear pattern extraction algorithm on the two-dimensional Range-Doppler map. In this context, the two-dimensional Range-Doppler map comprises detections from at least one target, at least one first-order ghost, and at least one second-order ghost with respect to one wall reflector.

    Dynamically doped field-effect transistor and a method for controlling such
    82.
    发明授权
    Dynamically doped field-effect transistor and a method for controlling such 有权

    公开(公告)号：US12154979B2

    公开(公告)日：2024-11-26

    申请号：US17496186

    申请日：2021-10-07

    Applicant: IMEC VZW

    Inventor： Aryan Afzalian

    IPC: H01L29/772 ,  H03K17/687

    Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.

    Method of producing a gate cut in a semiconductor component
    83.
    发明授权
    Method of producing a gate cut in a semiconductor component 有权

    公开(公告)号：US12154830B2

    公开(公告)日：2024-11-26

    申请号：US17580020

    申请日：2022-01-20

    Applicant: IMEC vzw

    Inventor： Gaspard Hiblot ,  Anshul Gupta ,  Geert Van Der Plas

    IPC: H01L21/8234 ,  H01L27/088

    Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

    METHOD FOR MANUFACTURING A NON-FLAT DEVICE BY DEFORMATION OF A FLAT DEVICE LAMINATE
    84.
    发明申请
    METHOD FOR MANUFACTURING A NON-FLAT DEVICE BY DEFORMATION OF A FLAT DEVICE LAMINATE 有权

    公开(公告)号：US20240383187A1

    公开(公告)日：2024-11-21

    申请号：US18693050

    申请日：2022-09-20

    Applicant: IMEC VZW ,  Universiteit Gent

    Inventor： Behnam MADADNIA ,  Jan VANFLETEREN ,  Frederick BOSSUYT

    IPC: B29C51/14 ,  B29K75/00 ,  B29K105/20 ,  B29L31/34 ,  B32B3/30 ,  B32B7/12 ,  B32B27/08 ,  B32B27/40 ,  H01L33/62

    Abstract: The disclosure relates to a method for manufacturing a shape-retaining non-flat device (100), comprising: providing (S10) a flat device laminate (200) comprising: a first layer of thermoformable material (210); a carrier layer (230); conductive traces (240) arranged at least on a second portion (232) of the carrier layer (230); a circuit element (250) arranged on the second portion (232) and electrically connected to the conductive traces (240); deforming (S20) the device region (260) of the flat device laminate (200) into the shape-retaining non-flat device (100) by thermoforming (S22) the flat device laminate (200), wherein the carrier layer (230) is non-stretchable such that the respective shortest distance (d), along the second portion (232) of the carrier layer (230), between the circuit element (250) and a first portion (231), prior to and after the step of deforming (S20) the flat device laminate (200), are equal.

    Method of operating a pore field-effect transistor sensor for detecting particles
    85.
    发明授权
    Method of operating a pore field-effect transistor sensor for detecting particles 有权

    公开(公告)号：US12146873B2

    公开(公告)日：2024-11-19

    申请号：US17849905

    申请日：2022-06-27

    Applicant: IMEC VZW

    Inventor： Anne Verhulst ,  Pol Van Dorpe

    IPC: G01N15/06 ,  G01N15/01 ,  G01N33/487

    Abstract: A method of operating a pore field-effect transistor (FET) sensor for detecting particles, wherein the pore FET sensor comprises a FET wherein a gate is controlled by a pore filled by a fluid, comprises: controlling a first voltage (Vcis) to set the FET in a subthreshold region; controlling a second voltage (Vtrans) to set a voltage difference between the first and second voltages (Vtrans) such that an effective difference in gate voltage experienced between a minimum and a maximum effective gate voltage during movement of a particle in the fluid is at least kT/q; and detecting a drain-source current in the FET, wherein the particle passing through the pore modulates the drain-source current for detecting presence of the particle.

    Device and Method for Collecting and Cleaning Solid Substances
    87.
    发明公开
    Device and Method for Collecting and Cleaning Solid Substances 审中-公开

    公开(公告)号：US20240287775A1

    公开(公告)日：2024-08-29

    申请号：US18589240

    申请日：2024-02-27

    Applicant: Stichting IMEC Nederland

    Inventor： Rogier Schoeman ,  Neil Mc Sharry

    IPC: E03C1/264 ,  B08B1/50 ,  B08B3/04 ,  B08B3/06

    CPC classification number: E03C1/264 ,  B08B1/50 ,  B08B3/045 ,  B08B3/06

    Abstract: Example embodiments relate to devices and methods for collecting and cleaning solid substances. An example device is provided for cleaning dirt particles from a solid body. The device includes a driving shaft configured to rotate along a rotational direction. The device also includes a container arrangement that includes a first slotted container. Further, the device includes a second slotted container attached to the first slotted container and to the driving shaft via a fitting arrangement. The fitting arrangement is configured to simultaneously rotate the second slotted container within the first slotted container in a direction opposite to the rotational direction of the driving shaft.

    CFET CELL ARCHITECTURE WITH A SIDE-ROUTING STRUCTURE
    89.
    发明公开
    CFET CELL ARCHITECTURE WITH A SIDE-ROUTING STRUCTURE 审中-公开

    公开(公告)号：US20240266349A1

    公开(公告)日：2024-08-08

    申请号：US18433779

    申请日：2024-02-06

    Applicant: IMEC VZW

    Inventor： Gioele Mirabelli ,  Juergen Boemmels ,  Julien Ryckaert

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/06 ,  H10B10/00

    CPC classification number: H01L27/092 ,  H01L23/5286 ,  H01L27/0688 ,  H10B10/12

    Abstract: This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

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